1*6dd67e32Sgdamore /* $NetBSD: aupcmciavar.h,v 1.1 2006/02/23 03:49:28 gdamore Exp $ */ 2*6dd67e32Sgdamore 3*6dd67e32Sgdamore /*- 4*6dd67e32Sgdamore * Copyright (c) 2006 Itronix Inc. 5*6dd67e32Sgdamore * All rights reserved. 6*6dd67e32Sgdamore * 7*6dd67e32Sgdamore * Written by Garrett D'Amore for Itronix Inc. 8*6dd67e32Sgdamore * 9*6dd67e32Sgdamore * Redistribution and use in source and binary forms, with or without 10*6dd67e32Sgdamore * modification, are permitted provided that the following conditions 11*6dd67e32Sgdamore * are met: 12*6dd67e32Sgdamore * 1. Redistributions of source code must retain the above copyright 13*6dd67e32Sgdamore * notice, this list of conditions and the following disclaimer. 14*6dd67e32Sgdamore * 2. Redistributions in binary form must reproduce the above copyright 15*6dd67e32Sgdamore * notice, this list of conditions and the following disclaimer in the 16*6dd67e32Sgdamore * documentation and/or other materials provided with the distribution. 17*6dd67e32Sgdamore * 3. The name of Itronix Inc. may not be used to endorse 18*6dd67e32Sgdamore * or promote products derived from this software without specific 19*6dd67e32Sgdamore * prior written permission. 20*6dd67e32Sgdamore * 21*6dd67e32Sgdamore * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22*6dd67e32Sgdamore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23*6dd67e32Sgdamore * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24*6dd67e32Sgdamore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25*6dd67e32Sgdamore * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26*6dd67e32Sgdamore * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27*6dd67e32Sgdamore * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28*6dd67e32Sgdamore * ON ANY THEORY OF LIABILITY, WHETHER IN 29*6dd67e32Sgdamore * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30*6dd67e32Sgdamore * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31*6dd67e32Sgdamore * POSSIBILITY OF SUCH DAMAGE. 32*6dd67e32Sgdamore */ 33*6dd67e32Sgdamore 34*6dd67e32Sgdamore #ifndef _MIPS_ALCHEMY_DEV_AUPCMCIAVAR_H 35*6dd67e32Sgdamore #define _MIPS_ALCHEMY_DEV_AUPCMCIAVAR_H 36*6dd67e32Sgdamore 37*6dd67e32Sgdamore #define AUPCMCIA_NWINS 16 38*6dd67e32Sgdamore #define AUPCMCIA_NSLOTS 2 /* current boards only have two slots */ 39*6dd67e32Sgdamore 40*6dd67e32Sgdamore #define AUPCMCIA_IRQ_CARD 0 41*6dd67e32Sgdamore #define AUPCMCIA_IRQ_INSERT 1 42*6dd67e32Sgdamore #define AUPCMCIA_MAP_SIZE 16 * 1024 * 1024 /* arbitrary */ 43*6dd67e32Sgdamore 44*6dd67e32Sgdamore struct aupcmcia_machdep { 45*6dd67e32Sgdamore int am_nslots; 46*6dd67e32Sgdamore bus_size_t (*am_slot_offset)(int); 47*6dd67e32Sgdamore int (*am_slot_irq)(int, int); 48*6dd67e32Sgdamore void (*am_slot_enable)(int); 49*6dd67e32Sgdamore void (*am_slot_disable)(int); 50*6dd67e32Sgdamore int (*am_slot_status)(int); 51*6dd67e32Sgdamore const char * (*am_slot_name)(int); 52*6dd67e32Sgdamore }; 53*6dd67e32Sgdamore 54*6dd67e32Sgdamore /* 55*6dd67e32Sgdamore * Machdep code must implement this to supply its slot implementation 56*6dd67e32Sgdamore * details to the framework. The address 57*6dd67e32Sgdamore */ 58*6dd67e32Sgdamore struct aupcmcia_machdep *aupcmcia_machdep(void); 59*6dd67e32Sgdamore 60*6dd67e32Sgdamore #endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */ 61