1*d3e53912Sdyoung /* $NetBSD: aupcivar.h,v 1.3 2011/04/04 20:37:51 dyoung Exp $ */ 20a8bdb27Sgdamore 30a8bdb27Sgdamore /*- 40a8bdb27Sgdamore * Copyright (c) 2006 Itronix Inc. 50a8bdb27Sgdamore * All rights reserved. 60a8bdb27Sgdamore * 70a8bdb27Sgdamore * Written by Garrett D'Amore for Itronix Inc. 80a8bdb27Sgdamore * 90a8bdb27Sgdamore * Redistribution and use in source and binary forms, with or without 100a8bdb27Sgdamore * modification, are permitted provided that the following conditions 110a8bdb27Sgdamore * are met: 120a8bdb27Sgdamore * 1. Redistributions of source code must retain the above copyright 130a8bdb27Sgdamore * notice, this list of conditions and the following disclaimer. 140a8bdb27Sgdamore * 2. Redistributions in binary form must reproduce the above copyright 150a8bdb27Sgdamore * notice, this list of conditions and the following disclaimer in the 160a8bdb27Sgdamore * documentation and/or other materials provided with the distribution. 170a8bdb27Sgdamore * 3. The name of Itronix Inc. may not be used to endorse 180a8bdb27Sgdamore * or promote products derived from this software without specific 190a8bdb27Sgdamore * prior written permission. 200a8bdb27Sgdamore * 210a8bdb27Sgdamore * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 220a8bdb27Sgdamore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 230a8bdb27Sgdamore * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 240a8bdb27Sgdamore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 250a8bdb27Sgdamore * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 260a8bdb27Sgdamore * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 270a8bdb27Sgdamore * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 280a8bdb27Sgdamore * ON ANY THEORY OF LIABILITY, WHETHER IN 290a8bdb27Sgdamore * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 300a8bdb27Sgdamore * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 310a8bdb27Sgdamore * POSSIBILITY OF SUCH DAMAGE. 320a8bdb27Sgdamore */ 330a8bdb27Sgdamore 340a8bdb27Sgdamore #ifndef _MIPS_ALCHEMY_DEV_AUPCIVAR_H 350a8bdb27Sgdamore #define _MIPS_ALCHEMY_DEV_AUPCIVAR_H 360a8bdb27Sgdamore 370a8bdb27Sgdamore #include <dev/pci/pcivar.h> 380a8bdb27Sgdamore 390a8bdb27Sgdamore /* 40e5312db1Sgdamore * PCI configuration space encompasses all 32-bits. 41e5312db1Sgdamore * 42e5312db1Sgdamore * PCI memory space encompasses all 32-bits, excepting that portion of 43e5312db1Sgdamore * the address space that is decoded by the Alchemy core for accesses 44e5312db1Sgdamore * to host memory. (That range is determined dynamically.) 45e5312db1Sgdamore * 46e5312db1Sgdamore * PCI I/O address range. We want to start offset from zero to avoid 47e5312db1Sgdamore * potential problems with devices. These addresses do not 48e5312db1Sgdamore * participate on the Alchemy system bus, hence we can choose any 49e5312db1Sgdamore * range we like. 16 MB is plenty. 50e5312db1Sgdamore */ 51e5312db1Sgdamore 52e5312db1Sgdamore #define AUPCI_IO_START 0x1000000 53e5312db1Sgdamore #define AUPCI_IO_END 0x1FFFFFF 54e5312db1Sgdamore 55e5312db1Sgdamore 56e5312db1Sgdamore /* 570a8bdb27Sgdamore * Machdep code must implement this. Stores an IRQ number in 580a8bdb27Sgdamore * pci_intr_handle_t. See pci_intr_map(9) for more detail. Returns 0 590a8bdb27Sgdamore * on success, non-zero on failure. 600a8bdb27Sgdamore */ 61*d3e53912Sdyoung int aupci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 620a8bdb27Sgdamore 630a8bdb27Sgdamore #endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */ 64