xref: /netbsd-src/sys/arch/mips/alchemy/dev/aupci.c (revision aec6f0cf2ee0e8ce1a23f9d46109cdee745ca66f)
1*aec6f0cfSskrll /* $NetBSD: aupci.c,v 1.22 2022/09/29 07:00:46 skrll Exp $ */
20a8bdb27Sgdamore 
30a8bdb27Sgdamore /*-
40a8bdb27Sgdamore  * Copyright (c) 2006 Itronix Inc.
50a8bdb27Sgdamore  * All rights reserved.
60a8bdb27Sgdamore  *
70a8bdb27Sgdamore  * Written by Garrett D'Amore for Itronix Inc.
80a8bdb27Sgdamore  *
90a8bdb27Sgdamore  * Redistribution and use in source and binary forms, with or without
100a8bdb27Sgdamore  * modification, are permitted provided that the following conditions
110a8bdb27Sgdamore  * are met:
120a8bdb27Sgdamore  * 1. Redistributions of source code must retain the above copyright
130a8bdb27Sgdamore  *    notice, this list of conditions and the following disclaimer.
140a8bdb27Sgdamore  * 2. Redistributions in binary form must reproduce the above copyright
150a8bdb27Sgdamore  *    notice, this list of conditions and the following disclaimer in the
160a8bdb27Sgdamore  *    documentation and/or other materials provided with the distribution.
170a8bdb27Sgdamore  * 3. The name of Itronix Inc. may not be used to endorse
180a8bdb27Sgdamore  *    or promote products derived from this software without specific
190a8bdb27Sgdamore  *    prior written permission.
200a8bdb27Sgdamore  *
210a8bdb27Sgdamore  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
220a8bdb27Sgdamore  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
230a8bdb27Sgdamore  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
240a8bdb27Sgdamore  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
250a8bdb27Sgdamore  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
260a8bdb27Sgdamore  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
270a8bdb27Sgdamore  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
280a8bdb27Sgdamore  * ON ANY THEORY OF LIABILITY, WHETHER IN
290a8bdb27Sgdamore  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
300a8bdb27Sgdamore  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
310a8bdb27Sgdamore  * POSSIBILITY OF SUCH DAMAGE.
320a8bdb27Sgdamore  */
330a8bdb27Sgdamore 
340a8bdb27Sgdamore #include "opt_pci.h"
350a8bdb27Sgdamore #include "pci.h"
360a8bdb27Sgdamore 
370a8bdb27Sgdamore #include <sys/cdefs.h>
38*aec6f0cfSskrll __KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.22 2022/09/29 07:00:46 skrll Exp $");
390a8bdb27Sgdamore 
400a8bdb27Sgdamore #include <sys/types.h>
410a8bdb27Sgdamore #include <sys/param.h>
420a8bdb27Sgdamore #include <sys/time.h>
430a8bdb27Sgdamore #include <sys/systm.h>
440a8bdb27Sgdamore #include <sys/errno.h>
450a8bdb27Sgdamore #include <sys/device.h>
46914f086dSmatt #include <sys/bus.h>
470a8bdb27Sgdamore 
480a8bdb27Sgdamore #include <uvm/uvm_extern.h>
490a8bdb27Sgdamore 
50914f086dSmatt #include <mips/locore.h>
51914f086dSmatt #include <mips/pte.h>
520a8bdb27Sgdamore 
530a8bdb27Sgdamore #include <dev/pci/pcivar.h>
540a8bdb27Sgdamore #include <dev/pci/pcireg.h>
550a8bdb27Sgdamore #include <dev/pci/pciconf.h>
560a8bdb27Sgdamore 
570a8bdb27Sgdamore #ifdef	PCI_NETBSD_CONFIGURE
580a8bdb27Sgdamore #include <mips/cache.h>
590a8bdb27Sgdamore #endif
600a8bdb27Sgdamore 
61e5312db1Sgdamore #include <mips/alchemy/include/au_himem_space.h>
620a8bdb27Sgdamore #include <mips/alchemy/include/aubusvar.h>
630a8bdb27Sgdamore #include <mips/alchemy/include/aureg.h>
640a8bdb27Sgdamore #include <mips/alchemy/include/auvar.h>
650a8bdb27Sgdamore 
660a8bdb27Sgdamore #include <mips/alchemy/dev/aupcireg.h>
670a8bdb27Sgdamore #include <mips/alchemy/dev/aupcivar.h>
680a8bdb27Sgdamore 
690a8bdb27Sgdamore struct aupci_softc {
70f58fcf6aSkiyohara 	device_t			sc_dev;
710a8bdb27Sgdamore 	struct mips_pci_chipset		sc_pc;
720a8bdb27Sgdamore 	struct mips_bus_space		sc_mem_space;
730a8bdb27Sgdamore 	struct mips_bus_space		sc_io_space;
74e5312db1Sgdamore 	struct mips_bus_space		sc_cfg_space;
750a8bdb27Sgdamore 
760a8bdb27Sgdamore 	bus_space_tag_t			sc_memt;
770a8bdb27Sgdamore 	bus_space_tag_t			sc_iot;
78e5312db1Sgdamore 	bus_space_tag_t			sc_cfgt;
790a8bdb27Sgdamore 
800a8bdb27Sgdamore 	bus_space_tag_t			sc_bust;
810a8bdb27Sgdamore 
820a8bdb27Sgdamore 	bus_space_handle_t		sc_bush;
830a8bdb27Sgdamore 	paddr_t				sc_cfgbase;
840a8bdb27Sgdamore 	paddr_t				sc_membase;
850a8bdb27Sgdamore 	paddr_t				sc_iobase;
860a8bdb27Sgdamore 
870a8bdb27Sgdamore 	/* XXX: dma tag */
880a8bdb27Sgdamore };
890a8bdb27Sgdamore 
90f58fcf6aSkiyohara int		aupcimatch(device_t, struct cfdata *, void *);
91f58fcf6aSkiyohara void		aupciattach(device_t, device_t, void *);
920a8bdb27Sgdamore 
930a8bdb27Sgdamore #if NPCI > 0
94f58fcf6aSkiyohara static void aupci_attach_hook(device_t, device_t, struct pcibus_attach_args *);
950a8bdb27Sgdamore static int aupci_bus_maxdevs(void *, int);
960a8bdb27Sgdamore static pcitag_t aupci_make_tag(void *, int, int, int);
970a8bdb27Sgdamore static void aupci_decompose_tag(void *, pcitag_t, int *, int *, int *);
980a8bdb27Sgdamore static pcireg_t aupci_conf_read(void *, pcitag_t, int);
990a8bdb27Sgdamore static void aupci_conf_write(void *, pcitag_t, int, pcireg_t);
100e58a356cSchristos static const char *aupci_intr_string(void *, pci_intr_handle_t, char *, size_t);
1010a8bdb27Sgdamore static void aupci_conf_interrupt(void *, int, int, int, int, int *);
1020a8bdb27Sgdamore static void *aupci_intr_establish(void *, pci_intr_handle_t, int,
1030a8bdb27Sgdamore     int (*)(void *), void *);
1040a8bdb27Sgdamore static void aupci_intr_disestablish(void *, void *);
1050a8bdb27Sgdamore 
1060a8bdb27Sgdamore #define	PCI_CFG_READ	0
1070a8bdb27Sgdamore #define	PCI_CFG_WRITE	1
1080a8bdb27Sgdamore 
109ca8ce3aeSthorpej #define	PCI_IO_START	AUPCI_IO_START
110ca8ce3aeSthorpej #define	PCI_IO_END	AUPCI_IO_END
111ca8ce3aeSthorpej #define	PCI_IO_SIZE	((PCI_IO_END - PCI_IO_START) + 1)
112ca8ce3aeSthorpej 
113ca8ce3aeSthorpej #define	PCI_MEM_END	0xffffffff
114ca8ce3aeSthorpej #define	PCI_MEM_SIZE(m)	((PCI_MEM_END - (m)) + 1)
115ca8ce3aeSthorpej 
1160a8bdb27Sgdamore #endif	/* NPCI > 0 */
1170a8bdb27Sgdamore 
118f58fcf6aSkiyohara CFATTACH_DECL_NEW(aupci, sizeof(struct aupci_softc),
1190a8bdb27Sgdamore     aupcimatch, aupciattach, NULL, NULL);
1200a8bdb27Sgdamore 
1210a8bdb27Sgdamore int aupci_found = 0;
1220a8bdb27Sgdamore 
1230a8bdb27Sgdamore /*
1240a8bdb27Sgdamore  * Physical PCI addresses are 36-bits long, so we need to have
1250a8bdb27Sgdamore  * adequate storage space for them.
1260a8bdb27Sgdamore  */
1270a8bdb27Sgdamore #if NPCI > 0
1280a8bdb27Sgdamore #if !defined(_MIPS_PADDR_T_64BIT) && !defined(_LP64)
1290a8bdb27Sgdamore #error	"aupci requires 64 bit paddr_t!"
1300a8bdb27Sgdamore #endif
1310a8bdb27Sgdamore #endif
1320a8bdb27Sgdamore 
1330a8bdb27Sgdamore int
aupcimatch(device_t parent,struct cfdata * match,void * aux)134f58fcf6aSkiyohara aupcimatch(device_t parent, struct cfdata *match, void *aux)
1350a8bdb27Sgdamore {
1360a8bdb27Sgdamore 	struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
1370a8bdb27Sgdamore 
1380a8bdb27Sgdamore 	if (strcmp(aa->aa_name, "aupci") != 0)
1390a8bdb27Sgdamore 		return 0;
1400a8bdb27Sgdamore 
1410a8bdb27Sgdamore 	if (aupci_found)
1420a8bdb27Sgdamore 		return 0;
1430a8bdb27Sgdamore 
1440a8bdb27Sgdamore 	return 1;
1450a8bdb27Sgdamore }
1460a8bdb27Sgdamore 
1470a8bdb27Sgdamore void
aupciattach(device_t parent,device_t self,void * aux)148f58fcf6aSkiyohara aupciattach(device_t parent, device_t self, void *aux)
1490a8bdb27Sgdamore {
150f58fcf6aSkiyohara 	struct aupci_softc		*sc = device_private(self);
1510a8bdb27Sgdamore 	struct aubus_attach_args	*aa = (struct aubus_attach_args *)aux;
1520a8bdb27Sgdamore 	uint32_t			cfg;
1530a8bdb27Sgdamore #if NPCI > 0
15443518cacSgdamore 	uint32_t			mbar, mask;
15543518cacSgdamore 	bus_addr_t			mstart;
1560a8bdb27Sgdamore 	struct pcibus_attach_args	pba;
1570a8bdb27Sgdamore #endif
1580a8bdb27Sgdamore 
1590a8bdb27Sgdamore 	aupci_found = 1;
1600a8bdb27Sgdamore 
161f58fcf6aSkiyohara 	sc->sc_dev = self;
1620a8bdb27Sgdamore 	sc->sc_bust = aa->aa_st;
1630a8bdb27Sgdamore 	if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0,
1640a8bdb27Sgdamore 		&sc->sc_bush) != 0) {
165f58fcf6aSkiyohara 		aprint_error(": unable to map PCI registers\n");
1660a8bdb27Sgdamore 		return;
1670a8bdb27Sgdamore 	}
1680a8bdb27Sgdamore 
1690a8bdb27Sgdamore #if NPCI > 0
1700a8bdb27Sgdamore 	/*
171e5312db1Sgdamore 	 * These physical addresses are locked in on the CPUs we have
1720a8bdb27Sgdamore 	 * seen.  Perhaps these should be passed in via locators, thru
1730a8bdb27Sgdamore 	 * the configuration file.
1740a8bdb27Sgdamore 	 */
1750a8bdb27Sgdamore 	sc->sc_cfgbase = PCI_CONFIG_BASE;
1760a8bdb27Sgdamore 	sc->sc_membase = PCI_MEM_BASE;
1770a8bdb27Sgdamore 	sc->sc_iobase = PCI_IO_BASE;
1780a8bdb27Sgdamore #endif
1790a8bdb27Sgdamore 
1800a8bdb27Sgdamore 	/*
1810a8bdb27Sgdamore 	 * Configure byte swapping, as YAMON doesn't do it.  YAMON does take
1820a8bdb27Sgdamore 	 * care of most of the rest of the details (clocking, etc.), however.
1830a8bdb27Sgdamore 	 */
1840a8bdb27Sgdamore #if _BYTE_ORDER == _BIG_ENDIAN
1850a8bdb27Sgdamore 	/*
1860a8bdb27Sgdamore 	 * N.B.: This still doesn't do the DMA thing properly.  I have
1870a8bdb27Sgdamore 	 * not yet figured out how to get DMA access to work properly
1880a8bdb27Sgdamore 	 * without having bytes swapped while the processor is in
1890a8bdb27Sgdamore 	 * big-endian mode.  I'm not even sure that the Alchemy part
1900a8bdb27Sgdamore 	 * can do it without swapping the bytes (which would be a
1910a8bdb27Sgdamore 	 * bummer, since then only parts which had hardware detection
1920a8bdb27Sgdamore 	 * and swapping support would work without special hacks in
1930a8bdb27Sgdamore 	 * their drivers.)
1940a8bdb27Sgdamore 	 */
1950a8bdb27Sgdamore 	cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
1960a8bdb27Sgdamore 	    AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN |
1970a8bdb27Sgdamore 	    AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA;
1980a8bdb27Sgdamore #else
1990a8bdb27Sgdamore 	cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
2000a8bdb27Sgdamore 	    AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN;
2010a8bdb27Sgdamore #endif
2020a8bdb27Sgdamore 	bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg);
2030a8bdb27Sgdamore 
2040a8bdb27Sgdamore 	cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS);
2050a8bdb27Sgdamore 
206f58fcf6aSkiyohara 	aprint_normal(": Alchemy Host-PCI Bridge, %sMHz\n",
207f58fcf6aSkiyohara 	    (cfg & PCI_STATUS_66MHZ_SUPPORT) ? "66" : "33");
208f58fcf6aSkiyohara 	aprint_naive("\n");
2090a8bdb27Sgdamore 
2100a8bdb27Sgdamore #if NPCI > 0
2110a8bdb27Sgdamore 	/*
212e5312db1Sgdamore 	 * PCI configuration space.  Address in this bus are
213e5312db1Sgdamore 	 * orthogonal to other spaces.  We need to make the entire
214e5312db1Sgdamore 	 * 32-bit address space available.
2150a8bdb27Sgdamore 	 */
216e5312db1Sgdamore 	sc->sc_cfgt = &sc->sc_cfg_space;
217e5312db1Sgdamore 	au_himem_space_init(sc->sc_cfgt, "pcicfg", sc->sc_cfgbase,
218e5312db1Sgdamore 	    0x00000000, 0xffffffff, AU_HIMEM_SPACE_IO);
2190a8bdb27Sgdamore 
2200a8bdb27Sgdamore 	/*
221e5312db1Sgdamore 	 * Virtual PCI memory.  Configured so that we don't overlap
222e5312db1Sgdamore 	 * with PCI memory space.
223e5312db1Sgdamore 	 */
224e5312db1Sgdamore 	mask = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MWMASK);
225e5312db1Sgdamore 	mask >>= AUPCI_MWMASK_SHIFT;
226e5312db1Sgdamore 	mask <<= AUPCI_MWMASK_SHIFT;
227e5312db1Sgdamore 
228e5312db1Sgdamore 	mbar = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MBAR);
2297572f01aSgdamore 	mstart = (mbar & mask) + (~mask + 1);
230e5312db1Sgdamore 
231e5312db1Sgdamore 	sc->sc_memt = &sc->sc_mem_space;
232e5312db1Sgdamore 	au_himem_space_init(sc->sc_memt, "pcimem", sc->sc_membase,
23343518cacSgdamore 	    mstart, 0xffffffff, AU_HIMEM_SPACE_LITTLE_ENDIAN);
234e5312db1Sgdamore 
235e5312db1Sgdamore 	/*
236e5312db1Sgdamore 	 * IO space.  Address in this bus are orthogonal to other spaces.
237e5312db1Sgdamore 	 * 16 MB should be plenty.  We don't start from zero to avoid
238e5312db1Sgdamore 	 * potential device bugs.
2390a8bdb27Sgdamore 	 */
2400a8bdb27Sgdamore 	sc->sc_iot = &sc->sc_io_space;
241e5312db1Sgdamore 	au_himem_space_init(sc->sc_iot, "pciio",
242e5312db1Sgdamore 	    sc->sc_iobase, AUPCI_IO_START, AUPCI_IO_END,
243e5312db1Sgdamore 	    AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO);
2440a8bdb27Sgdamore 
2450a8bdb27Sgdamore 	sc->sc_pc.pc_conf_v = sc;
2460a8bdb27Sgdamore 	sc->sc_pc.pc_attach_hook = aupci_attach_hook;
2470a8bdb27Sgdamore 	sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs;
2480a8bdb27Sgdamore 	sc->sc_pc.pc_make_tag = aupci_make_tag;
2490a8bdb27Sgdamore 	sc->sc_pc.pc_decompose_tag = aupci_decompose_tag;
2500a8bdb27Sgdamore 	sc->sc_pc.pc_conf_read = aupci_conf_read;
2510a8bdb27Sgdamore 	sc->sc_pc.pc_conf_write = aupci_conf_write;
2520a8bdb27Sgdamore 
2530a8bdb27Sgdamore 	sc->sc_pc.pc_intr_v = sc;
2540a8bdb27Sgdamore 	sc->sc_pc.pc_intr_map = aupci_intr_map;
2550a8bdb27Sgdamore 	sc->sc_pc.pc_intr_string = aupci_intr_string;
2560a8bdb27Sgdamore 	sc->sc_pc.pc_intr_establish = aupci_intr_establish;
2570a8bdb27Sgdamore 	sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish;
2580a8bdb27Sgdamore 	sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt;
2590a8bdb27Sgdamore 
2600a8bdb27Sgdamore #ifdef PCI_NETBSD_CONFIGURE
261ca8ce3aeSthorpej 	struct pciconf_resources *pcires = pciconf_resource_init();
262e5312db1Sgdamore 
263ca8ce3aeSthorpej 	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
264ca8ce3aeSthorpej 	    PCI_IO_START, PCI_IO_SIZE);
265ca8ce3aeSthorpej 	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
266ca8ce3aeSthorpej 	    mstart, PCI_MEM_SIZE(mstart));
267e5312db1Sgdamore 
268ca8ce3aeSthorpej 	pci_configure_bus(&sc->sc_pc, pcires, 0,
269ca8ce3aeSthorpej 	    mips_cache_info.mci_dcache_align);
270ca8ce3aeSthorpej 	pciconf_resource_fini(pcires);
2710a8bdb27Sgdamore #endif
2720a8bdb27Sgdamore 
2730a8bdb27Sgdamore 	pba.pba_iot = sc->sc_iot;
2740a8bdb27Sgdamore 	pba.pba_memt = sc->sc_memt;
2750a8bdb27Sgdamore 	/* XXX: review dma tag logic */
2760a8bdb27Sgdamore 	pba.pba_dmat = aa->aa_dt;
2770a8bdb27Sgdamore 	pba.pba_dmat64 = NULL;
2780a8bdb27Sgdamore 	pba.pba_pc = &sc->sc_pc;
279a6b2b839Sdyoung 	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
2800a8bdb27Sgdamore 	pba.pba_bus = 0;
2810a8bdb27Sgdamore 	pba.pba_bridgetag = NULL;
2820a8bdb27Sgdamore 
283c7fb772bSthorpej 	config_found(self, &pba, pcibusprint, CFARGS_NONE);
2840a8bdb27Sgdamore #endif	/* NPCI > 0 */
2850a8bdb27Sgdamore }
2860a8bdb27Sgdamore 
2870a8bdb27Sgdamore #if NPCI > 0
2880a8bdb27Sgdamore 
2890a8bdb27Sgdamore void
aupci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)290f58fcf6aSkiyohara aupci_attach_hook(device_t parent, device_t self,
2910a8bdb27Sgdamore     struct pcibus_attach_args *pba)
2920a8bdb27Sgdamore {
2930a8bdb27Sgdamore }
2940a8bdb27Sgdamore 
2950a8bdb27Sgdamore int
aupci_bus_maxdevs(void * v,int busno)2960a8bdb27Sgdamore aupci_bus_maxdevs(void *v, int busno)
2970a8bdb27Sgdamore {
2980a8bdb27Sgdamore 
2990a8bdb27Sgdamore 	return 32;
3000a8bdb27Sgdamore }
3010a8bdb27Sgdamore 
3020a8bdb27Sgdamore pcitag_t
aupci_make_tag(void * v,int bus,int device,int function)3030a8bdb27Sgdamore aupci_make_tag(void *v, int bus, int device, int function)
3040a8bdb27Sgdamore {
3050a8bdb27Sgdamore 	pcitag_t		tag;
3060a8bdb27Sgdamore 
3070a8bdb27Sgdamore 	if (bus >= 256 || device >= 32 || function >= 8)
3080a8bdb27Sgdamore 		panic("aupci_make_tag: bad request");
3090a8bdb27Sgdamore 
3100a8bdb27Sgdamore 	tag = (bus << 16) | (device << 11) | (function << 8);
3110a8bdb27Sgdamore 
3120a8bdb27Sgdamore 	return tag;
3130a8bdb27Sgdamore }
3140a8bdb27Sgdamore 
3150a8bdb27Sgdamore void
aupci_decompose_tag(void * v,pcitag_t tag,int * b,int * d,int * f)3160a8bdb27Sgdamore aupci_decompose_tag(void *v, pcitag_t tag, int *b, int *d, int *f)
3170a8bdb27Sgdamore {
3180a8bdb27Sgdamore 
3190a8bdb27Sgdamore 	if (b != NULL)
3200a8bdb27Sgdamore 		*b = (tag >> 16) & 0xff;
3210a8bdb27Sgdamore 	if (d != NULL)
3220a8bdb27Sgdamore 		*d = (tag >> 11) & 0x1f;
3230a8bdb27Sgdamore 	if (f != NULL)
3240a8bdb27Sgdamore 		*f = (tag >> 8) & 0x07;
3250a8bdb27Sgdamore }
3260a8bdb27Sgdamore 
327712239e3Sthorpej static inline bool
aupci_conf_access(void * v,int dir,pcitag_t tag,int reg,pcireg_t * datap)328e5312db1Sgdamore aupci_conf_access(void *v, int dir, pcitag_t tag, int reg, pcireg_t *datap)
3290a8bdb27Sgdamore {
3300a8bdb27Sgdamore 	struct aupci_softc	*sc = (struct aupci_softc *)v;
331e5312db1Sgdamore 	uint32_t		status;
332e5312db1Sgdamore 	int			s;
333e5312db1Sgdamore 	bus_addr_t		addr;
334e5312db1Sgdamore 	int			b, d, f;
335e5312db1Sgdamore 	bus_space_handle_t	h;
3360a8bdb27Sgdamore 
337605f564fSmsaitoh 	if ((unsigned int)reg >= PCI_CONF_SIZE)
338605f564fSmsaitoh 		return false;
339605f564fSmsaitoh 
3400a8bdb27Sgdamore 	aupci_decompose_tag(v, tag, &b, &d, &f);
3410a8bdb27Sgdamore 	if (b) {
3420a8bdb27Sgdamore 		/* configuration type 1 */
343e5312db1Sgdamore 		addr = 0x80000000 | tag;
3440a8bdb27Sgdamore 	} else if (d > 19) {
3450a8bdb27Sgdamore 		/* device num too big for bus 0 */
34609c5f9ccSthorpej 		return false;
3470a8bdb27Sgdamore 	} else {
348e5312db1Sgdamore 		addr = (0x800 << d) | (f << 8);
3490a8bdb27Sgdamore 	}
3500a8bdb27Sgdamore 
3510a8bdb27Sgdamore 	/* probing illegal target is OK, return an error indication */
352e5312db1Sgdamore 	if (addr == 0)
35309c5f9ccSthorpej 		return false;
3540a8bdb27Sgdamore 
355e5312db1Sgdamore 	if (bus_space_map(sc->sc_cfgt, addr, 256, 0, &h) != 0)
35609c5f9ccSthorpej 		return false;
3570a8bdb27Sgdamore 
3580a8bdb27Sgdamore 	s = splhigh();
3590a8bdb27Sgdamore 
3600a8bdb27Sgdamore 	if (dir == PCI_CFG_WRITE)
361e5312db1Sgdamore 		bus_space_write_4(sc->sc_cfgt, h, reg, *datap);
3620a8bdb27Sgdamore 	else
363e5312db1Sgdamore 		*datap = bus_space_read_4(sc->sc_cfgt, h, reg);
3640a8bdb27Sgdamore 
3650a8bdb27Sgdamore 	DELAY(2);
3660a8bdb27Sgdamore 
3670a8bdb27Sgdamore 	/* check for and clear master abort condition */
3680a8bdb27Sgdamore 	status = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG);
3690a8bdb27Sgdamore 	bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG,
3700a8bdb27Sgdamore 	    status & ~(AUPCI_CONFIG_EF));
3710a8bdb27Sgdamore 
37234cdf29cSsimonb 	splx(s);
3730a8bdb27Sgdamore 
374e5312db1Sgdamore 	bus_space_unmap(sc->sc_cfgt, h, 256);
375e5312db1Sgdamore 
376e5312db1Sgdamore 	/* if we got a PCI master abort, fail it */
377e5312db1Sgdamore 	if (status & AUPCI_CONFIG_EF)
37809c5f9ccSthorpej 		return false;
379e5312db1Sgdamore 
38009c5f9ccSthorpej 	return true;
3810a8bdb27Sgdamore }
3820a8bdb27Sgdamore 
3830a8bdb27Sgdamore pcireg_t
aupci_conf_read(void * v,pcitag_t tag,int reg)3840a8bdb27Sgdamore aupci_conf_read(void *v, pcitag_t tag, int reg)
3850a8bdb27Sgdamore {
3860a8bdb27Sgdamore 	pcireg_t		data;
3870a8bdb27Sgdamore 
38809c5f9ccSthorpej 	if (aupci_conf_access(v, PCI_CFG_READ, tag, reg, &data) == false)
3890a8bdb27Sgdamore 		return 0xffffffff;
3900a8bdb27Sgdamore 
3910a8bdb27Sgdamore 	return (data);
3920a8bdb27Sgdamore }
3930a8bdb27Sgdamore 
3940a8bdb27Sgdamore void
aupci_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)3950a8bdb27Sgdamore aupci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
3960a8bdb27Sgdamore {
3970a8bdb27Sgdamore 
3980a8bdb27Sgdamore 	aupci_conf_access(v, PCI_CFG_WRITE, tag, reg, &data);
3990a8bdb27Sgdamore }
4000a8bdb27Sgdamore 
4010a8bdb27Sgdamore const char *
aupci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)402e58a356cSchristos aupci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
4030a8bdb27Sgdamore {
404e58a356cSchristos 	snprintf(buf, len, "irq %u", (unsigned)ih);
405e58a356cSchristos 	return buf;
4060a8bdb27Sgdamore }
4070a8bdb27Sgdamore 
4080a8bdb27Sgdamore void *
aupci_intr_establish(void * v,pci_intr_handle_t ih,int ipl,int (* handler)(void *),void * arg)4090a8bdb27Sgdamore aupci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
4100a8bdb27Sgdamore     int (*handler)(void *), void *arg)
4110a8bdb27Sgdamore {
4120a8bdb27Sgdamore 
4130a8bdb27Sgdamore 	return (au_intr_establish(ih, 0, ipl, IST_LEVEL_LOW, handler, arg));
4140a8bdb27Sgdamore }
4150a8bdb27Sgdamore 
4160a8bdb27Sgdamore void
aupci_intr_disestablish(void * v,void * cookie)4170a8bdb27Sgdamore aupci_intr_disestablish(void *v, void *cookie)
4180a8bdb27Sgdamore {
4190a8bdb27Sgdamore 
4200a8bdb27Sgdamore 	au_intr_disestablish(cookie);
4210a8bdb27Sgdamore }
4220a8bdb27Sgdamore 
4230a8bdb27Sgdamore void
aupci_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * iline)4240a8bdb27Sgdamore aupci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline)
4250a8bdb27Sgdamore {
4260a8bdb27Sgdamore 	/*
4270a8bdb27Sgdamore 	 * We let the machdep_pci_intr_map take care of IRQ routing.
4280a8bdb27Sgdamore 	 * On some platforms the BIOS may have handled this properly,
4290a8bdb27Sgdamore 	 * on others it might not have.  For now we avoid clobbering
4300a8bdb27Sgdamore 	 * the settings establishsed by the BIOS, so that they will be
4310a8bdb27Sgdamore 	 * there if the platform logic is confident that it can rely
4320a8bdb27Sgdamore 	 * on them.
4330a8bdb27Sgdamore 	 */
4340a8bdb27Sgdamore }
4350a8bdb27Sgdamore 
4360a8bdb27Sgdamore #endif
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