xref: /netbsd-src/sys/arch/macppc/dev/if_bmreg.h (revision 6b26a49ee93b563a860e5f09e132e063ab50734f)
1*6b26a49eStsubai /*	$NetBSD: if_bmreg.h,v 1.2 2000/01/25 14:38:50 tsubai Exp $	*/
213529d18Stsubai 
313529d18Stsubai /*
413529d18Stsubai  * Copyright 1991-1998 by Open Software Foundation, Inc.
513529d18Stsubai  *              All Rights Reserved
613529d18Stsubai  *
713529d18Stsubai  * Permission to use, copy, modify, and distribute this software and
813529d18Stsubai  * its documentation for any purpose and without fee is hereby granted,
913529d18Stsubai  * provided that the above copyright notice appears in all copies and
1013529d18Stsubai  * that both the copyright notice and this permission notice appear in
1113529d18Stsubai  * supporting documentation.
1213529d18Stsubai  *
1313529d18Stsubai  * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
1413529d18Stsubai  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
1513529d18Stsubai  * FOR A PARTICULAR PURPOSE.
1613529d18Stsubai  *
1713529d18Stsubai  * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
1813529d18Stsubai  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
1913529d18Stsubai  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
2013529d18Stsubai  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
2113529d18Stsubai  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2213529d18Stsubai  */
2313529d18Stsubai 
2413529d18Stsubai /* -------------------------------------------------------------------- */
2513529d18Stsubai /* Heathrow (F)eature (C)ontrol (R)egister Addresses			*/
2613529d18Stsubai /* -------------------------------------------------------------------- */
2713529d18Stsubai #define EnetEnable	0x60000000	/* enable Enet Xcvr/Controller */
2813529d18Stsubai #define ResetEnetCell	0x80000000	/* reset Enet cell */
2913529d18Stsubai 
3013529d18Stsubai /* -------------------------------------------------------------------- */
3113529d18Stsubai /*	BigMac Register Numbers & Bit Assignments			*/
3213529d18Stsubai /* -------------------------------------------------------------------- */
3313529d18Stsubai #define XIFC		0x0000
3413529d18Stsubai #define  TxOutputEnable		0x0001
3513529d18Stsubai #define  MIILoopbackBits	0x0006
3613529d18Stsubai #define  MIIBufferEnable	0x0008
3713529d18Stsubai #define  SQETestEnable		0x0010
3813529d18Stsubai #define LinkStatus	0x0100
3913529d18Stsubai #define TXFIFOCSR	0x0100
4013529d18Stsubai #define  TxFIFOEnable		0x0001
4113529d18Stsubai #define  TxFIFO128		0x0000
4213529d18Stsubai #define TXTH		0x0110
4313529d18Stsubai #define RXFIFOCSR	0x0120
4413529d18Stsubai #define  RxFIFOEnable		TxFIFOEnable
4513529d18Stsubai #define  RxFIFO128		TxFIFO128
4613529d18Stsubai #define MEMADD		0x0130
4713529d18Stsubai #define MEMDATAHI	0x0140
4813529d18Stsubai #define MEMDATALO	0x0150
4913529d18Stsubai #define XCVRIF		0x0160
5013529d18Stsubai #define  COLActiveLow		0x0002
5113529d18Stsubai #define  SerialMode		0x0004
5213529d18Stsubai #define  ClkBit			0x0008
5313529d18Stsubai #define CHIPID		0x0170
5413529d18Stsubai #define MIFCSR		0x0180
55*6b26a49eStsubai #define  MIFDC			0x0001	/* MII clock */
56*6b26a49eStsubai #define  MIFDO			0x0002	/* MII data out */
57*6b26a49eStsubai #define  MIFDIR			0x0004	/* MII direction (1: write) */
58*6b26a49eStsubai #define  MIFDI			0x0008	/* MII data in */
5913529d18Stsubai #define SROMCSR		0x0190
6013529d18Stsubai #define TXPNTR		0x01A0
6113529d18Stsubai #define RXPNTR		0x01B0
6213529d18Stsubai #define STATUS		0x0200
6313529d18Stsubai #define INTDISABLE	0x0210
6413529d18Stsubai #define  IntFrameReceived	0x0001
6513529d18Stsubai #define  IntRxFrameCntExp	0x0002
6613529d18Stsubai #define  IntRxAlignCntExp	0x0004
6713529d18Stsubai #define  IntRxCRCCntExp		0x0008
6813529d18Stsubai #define  IntRxLenCntExp		0x0010
6913529d18Stsubai #define  IntRxOverFlow		0x0020
7013529d18Stsubai #define  IntRxCodeViolation	0x0040
7113529d18Stsubai #define  IntSQETestError	0x0080
7213529d18Stsubai #define  IntFrameSent		0x0100
7313529d18Stsubai #define  IntTxUnderrun		0x0200
7413529d18Stsubai #define  IntTxMaxSizeError	0x0400
7513529d18Stsubai #define  IntTxNormalCollExp	0x0800
7613529d18Stsubai #define  IntTxExcessCollExp	0x1000
7713529d18Stsubai #define  IntTxLateCollExp	0x2000
7813529d18Stsubai #define  IntTxNetworkCollExp	0x4000
7913529d18Stsubai #define  IntTxDeferTimerExp	0x8000
8013529d18Stsubai #define  NormalIntEvents	~(IntFrameSent)
8113529d18Stsubai #define  NoEventsMask		0xFFFF
8213529d18Stsubai 
8313529d18Stsubai #define TxNeverGiveUp	0x0400
8413529d18Stsubai #define TXRST		0x0420
8513529d18Stsubai #define  TxResetBit		0x0001
8613529d18Stsubai #define TXCFG		0x0430
8713529d18Stsubai #define  TxMACEnable		0x0001
8813529d18Stsubai #define  TxThreshold		0x0004
89*6b26a49eStsubai #define  TxFullDuplex		0x0200
9013529d18Stsubai #define IPG1		0x0440
9113529d18Stsubai #define IPG2		0x0450
9213529d18Stsubai #define ALIMIT		0x0460
9313529d18Stsubai #define SLOT		0x0470
9413529d18Stsubai #define PALEN		0x0480
9513529d18Stsubai #define PAPAT		0x0490
9613529d18Stsubai #define TXSFD		0x04A0
9713529d18Stsubai #define JAM		0x04B0
9813529d18Stsubai #define TXMAX		0x04C0
9913529d18Stsubai #define TXMIN		0x04D0
10013529d18Stsubai #define PAREG		0x04E0
10113529d18Stsubai #define DCNT		0x04F0
10213529d18Stsubai #define NCCNT		0x0500
10313529d18Stsubai #define NTCNT		0x0510
10413529d18Stsubai #define EXCNT		0x0520
10513529d18Stsubai #define LTCNT		0x0530
10613529d18Stsubai #define RSEED		0x0540
10713529d18Stsubai #define TXSM		0x0550
10813529d18Stsubai #define RXRST		0x0620
10913529d18Stsubai #define  RxResetValue		0x0000
11013529d18Stsubai #define RXCFG		0x0630
11113529d18Stsubai #define  RxMACEnable		0x0001
11213529d18Stsubai #define  ReservedValue		0x0004
11313529d18Stsubai #define  RxPromiscEnable	0x0040
11413529d18Stsubai #define  RxCRCEnable		0x0100
11513529d18Stsubai #define  RxRejectOwnPackets	0x0200
11613529d18Stsubai #define  RxHashFilterEnable	0x0800
11713529d18Stsubai #define  RxAddrFilterEnable	0x1000
11813529d18Stsubai #define RXMAX		0x0640
11913529d18Stsubai #define RXMIN		0x0650
12013529d18Stsubai #define MADD2		0x0660
12113529d18Stsubai #define MADD1		0x0670
12213529d18Stsubai #define MADD0		0x0680
12313529d18Stsubai #define FRCNT		0x0690
12413529d18Stsubai #define LECNT		0x06A0
12513529d18Stsubai #define AECNT		0x06B0
12613529d18Stsubai #define FECNT		0x06C0
12713529d18Stsubai #define RXSM		0x06D0
12813529d18Stsubai #define RXCV		0x06E0
12913529d18Stsubai #define HASH3		0x0700
13013529d18Stsubai #define HASH2		0x0710
13113529d18Stsubai #define HASH1		0x0720
13213529d18Stsubai #define HASH0		0x0730
13313529d18Stsubai #define AFR2		0x0740
13413529d18Stsubai #define AFR1		0x0750
13513529d18Stsubai #define AFR0		0x0760
13613529d18Stsubai #define AFCR		0x0770
13713529d18Stsubai #define  EnableAllCompares	0x0fff
13813529d18Stsubai 
13913529d18Stsubai /* -------------------------------------------------------------------- */
14013529d18Stsubai /*	Misc. Bit definitions for BMac Status word			*/
14113529d18Stsubai /* -------------------------------------------------------------------- */
14213529d18Stsubai #define RxAbortBit	0x8000	/* status bit in BMac status for rx packets */
14313529d18Stsubai #define RxLengthMask	0x3FFF	/* bits that determine length of rx packets */
14413529d18Stsubai 
14513529d18Stsubai #define NETWORK_BUFSIZE		(ETHERMAXPACKET + ETHERCRC + 2)
146