1*2883d9a6Stsutsui /* $NetBSD: board.h,v 1.2 2021/09/26 13:43:30 tsutsui Exp $ */ 23dd15d69Stsutsui /* $OpenBSD: board.h,v 1.15 2017/11/03 06:55:08 aoyama Exp $ */ 33dd15d69Stsutsui /* 43dd15d69Stsutsui * Mach Operating System 53dd15d69Stsutsui * Copyright (c) 1993-1991 Carnegie Mellon University 63dd15d69Stsutsui * Copyright (c) 1991 OMRON Corporation 73dd15d69Stsutsui * All Rights Reserved. 83dd15d69Stsutsui * 93dd15d69Stsutsui * Permission to use, copy, modify and distribute this software and its 103dd15d69Stsutsui * documentation is hereby granted, provided that both the copyright 113dd15d69Stsutsui * notice and this permission notice appear in all copies of the 123dd15d69Stsutsui * software, derivative works or modified versions, and any portions 133dd15d69Stsutsui * thereof, and that both notices appear in supporting documentation. 143dd15d69Stsutsui * 153dd15d69Stsutsui * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" 163dd15d69Stsutsui * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND 173dd15d69Stsutsui * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 183dd15d69Stsutsui * 193dd15d69Stsutsui * Carnegie Mellon requests users of this software to return to 203dd15d69Stsutsui * 213dd15d69Stsutsui * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 223dd15d69Stsutsui * School of Computer Science 233dd15d69Stsutsui * Carnegie Mellon University 243dd15d69Stsutsui * Pittsburgh PA 15213-3890 253dd15d69Stsutsui * 263dd15d69Stsutsui * any improvements or extensions that they make and grant Carnegie the 273dd15d69Stsutsui * rights to redistribute these changes. 283dd15d69Stsutsui */ 293dd15d69Stsutsui 303dd15d69Stsutsui #ifndef _MACHINE_BOARD_H_ 313dd15d69Stsutsui #define _MACHINE_BOARD_H_ 323dd15d69Stsutsui 333dd15d69Stsutsui /* 343dd15d69Stsutsui * OMRON SX9100DT CPU board constants 353dd15d69Stsutsui */ 363dd15d69Stsutsui 373dd15d69Stsutsui /* 383dd15d69Stsutsui * Something to put append a 'U' to a long constant if it's C so that 393dd15d69Stsutsui * it'll be unsigned in both ANSI and traditional. 403dd15d69Stsutsui */ 413dd15d69Stsutsui #if defined(_LOCORE) 423dd15d69Stsutsui #define U(num) num 433dd15d69Stsutsui #elif defined(__STDC__) 443dd15d69Stsutsui #define U(num) num ## U 453dd15d69Stsutsui #else 463dd15d69Stsutsui #define U(num) num/**/U 473dd15d69Stsutsui #endif 483dd15d69Stsutsui 493dd15d69Stsutsui #define PROM_ADDR U(0x41000000) /* PROM */ 503dd15d69Stsutsui #define PROM_SPACE U(0x00040000) 513dd15d69Stsutsui #define NVRAM_ADDR U(0x45000000) /* Non Volatile */ 523dd15d69Stsutsui #define NVRAM_SPACE U(0x00001FDC) 533dd15d69Stsutsui #define FUSE_ROM_ADDR U(0x43000000) /* FUSE_ROM */ 543dd15d69Stsutsui #define FUSE_ROM_SPACE 1024 553dd15d69Stsutsui #define OBIO_CLOCK_BASE U(0x45000000) /* Mostek or Dallas TimeKeeper */ 563dd15d69Stsutsui #define OBIO_PIO0_BASE U(0x49000000) /* PIO-0 */ 573dd15d69Stsutsui #define OBIO_PIO0_SPACE U(0x00000004) 583dd15d69Stsutsui #define OBIO_PIO0A U(0x49000000) /* PIO-0 port A */ 593dd15d69Stsutsui #define OBIO_PIO0B U(0x49000001) /* PIO-0 port B */ 603dd15d69Stsutsui #define OBIO_PIO0C U(0x49000002) /* PIO-0 port C*/ 613dd15d69Stsutsui #define OBIO_PIO0 U(0x49000003) /* PIO-0 control */ 623dd15d69Stsutsui #define OBIO_PIO1_BASE U(0x4D000000) /* PIO-1 */ 633dd15d69Stsutsui #define OBIO_PIO1_SPACE U(0x00000004) 643dd15d69Stsutsui #define OBIO_PIO1A U(0x4D000000) /* PIO-1 port A */ 653dd15d69Stsutsui #define OBIO_PIO1B U(0x4D000001) /* PIO-1 port B */ 663dd15d69Stsutsui #define OBIO_PIO1C U(0x4D000002) /* PIO-1 port C*/ 673dd15d69Stsutsui #define OBIO_PIO1 U(0x4D000003) /* PIO-1 control */ 683dd15d69Stsutsui #define OBIO_SIO U(0x51000000) /* SIO */ 693dd15d69Stsutsui #define OBIO_TAS U(0x61000000) /* TAS register */ 703dd15d69Stsutsui #define OBIO_CLOCK U(0x63000000) /* system clock */ 713dd15d69Stsutsui 723dd15d69Stsutsui #define TRI_PORT_RAM U(0x71000000) /* 3 port RAM */ 733dd15d69Stsutsui #define TRI_PORT_RAM_SPACE 0x20000 743dd15d69Stsutsui #define EXT_A_ADDR U(0x81000000) /* extension board A */ 753dd15d69Stsutsui #define EXT_A_SPACE U(0x02000000) 763dd15d69Stsutsui #define EXT_B_ADDR U(0x83000000) /* extension board B */ 773dd15d69Stsutsui #define EXT_B_SPACE U(0x01000000) 783dd15d69Stsutsui #define PC_BASE U(0x90000000) /* pc-98 extension board */ 793dd15d69Stsutsui #define PC_SPACE U(0x02000000) 803dd15d69Stsutsui 813dd15d69Stsutsui #define MROM_ADDR U(0xA1000000) /* Mask ROM address */ 823dd15d69Stsutsui #define MROM_SPACE 0x400000 833dd15d69Stsutsui #define BMAP_START U(0xB1000000) /* Bitmap start address */ 843dd15d69Stsutsui #define BMAP_SPACE (BMAP_END - BMAP_START) 853dd15d69Stsutsui #define BMAP_RFCNT U(0xB1000000) /* RFCNT register */ 863dd15d69Stsutsui #define BMAP_BMSEL U(0xB1040000) /* BMSEL register */ 873dd15d69Stsutsui #define BMAP_BMP U(0xB1080000) /* common bitmap plane */ 883dd15d69Stsutsui #define BMAP_BMAP0 U(0xB10C0000) /* bitmap plane 0 */ 893dd15d69Stsutsui #define BMAP_BMAP1 U(0xB1100000) /* bitmap plane 1 */ 903dd15d69Stsutsui #define BMAP_BMAP2 U(0xB1140000) /* bitmap plane 2 */ 913dd15d69Stsutsui #define BMAP_BMAP3 U(0xB1180000) /* bitmap plane 3 */ 923dd15d69Stsutsui #define BMAP_BMAP4 U(0xB11C0000) /* bitmap plane 4 */ 933dd15d69Stsutsui #define BMAP_BMAP5 U(0xB1200000) /* bitmap plane 5 */ 943dd15d69Stsutsui #define BMAP_BMAP6 U(0xB1240000) /* bitmap plane 6 */ 953dd15d69Stsutsui #define BMAP_BMAP7 U(0xB1280000) /* bitmap plane 7 */ 963dd15d69Stsutsui #define BMAP_FN U(0xB12C0000) /* common bitmap function */ 973dd15d69Stsutsui #define BMAP_FN0 U(0xB1300000) /* bitmap function 0 */ 983dd15d69Stsutsui #define BMAP_FN1 U(0xB1340000) /* bitmap function 1 */ 993dd15d69Stsutsui #define BMAP_FN2 U(0xB1380000) /* bitmap function 2 */ 1003dd15d69Stsutsui #define BMAP_FN3 U(0xB13C0000) /* bitmap function 3 */ 1013dd15d69Stsutsui #define BMAP_FN4 U(0xB1400000) /* bitmap function 4 */ 1023dd15d69Stsutsui #define BMAP_FN5 U(0xB1440000) /* bitmap function 5 */ 1033dd15d69Stsutsui #define BMAP_FN6 U(0xB1480000) /* bitmap function 6 */ 1043dd15d69Stsutsui #define BMAP_FN7 U(0xB14C0000) /* bitmap function 7 */ 1053dd15d69Stsutsui #define BMAP_END U(0xB1500000) 1063dd15d69Stsutsui #define BMAP_END24P U(0xB1800000) /* end of 24p framemem */ 1073dd15d69Stsutsui #define BMAP_PALLET0 U(0xC0000000) /* color pallet */ 1083dd15d69Stsutsui #define BMAP_PALLET1 U(0xC1000000) /* color pallet */ 1093dd15d69Stsutsui #define BMAP_PALLET2 U(0xC1100000) /* color pallet */ 1103dd15d69Stsutsui #define BOARD_CHECK_REG U(0xD0000000) /* board check register */ 1113dd15d69Stsutsui #define BMAP_CRTC U(0xD1000000) /* CRTC-II */ 1123dd15d69Stsutsui #define BMAP_IDENTROM U(0xD1800000) /* bitmap-board identify ROM */ 1133dd15d69Stsutsui #define SCSI_ADDR U(0xE1000000) /* SCSI address */ 1143dd15d69Stsutsui #define SCSI_2_ADDR U(0xE1000040) /* 2nd SCSI address */ 1153dd15d69Stsutsui #define LANCE_ADDR U(0xF1000000) /* LANCE */ 1163dd15d69Stsutsui 1173dd15d69Stsutsui #endif /* _MACHINE_BOARD_H_ */ 118