1*d6d9fbe2Sthorpej /* $NetBSD: opti82c558reg.h,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ 2*d6d9fbe2Sthorpej 3*d6d9fbe2Sthorpej /* 4*d6d9fbe2Sthorpej * Copyright (c) 1999, by UCHIYAMA Yasushi 5*d6d9fbe2Sthorpej * All rights reserved. 6*d6d9fbe2Sthorpej * 7*d6d9fbe2Sthorpej * Redistribution and use in source and binary forms, with or without 8*d6d9fbe2Sthorpej * modification, are permitted provided that the following conditions 9*d6d9fbe2Sthorpej * are met: 10*d6d9fbe2Sthorpej * 1. Redistributions of source code must retain the above copyright 11*d6d9fbe2Sthorpej * notice, this list of conditions and the following disclaimer. 12*d6d9fbe2Sthorpej * 2. The name of the developer may NOT be used to endorse or promote products 13*d6d9fbe2Sthorpej * derived from this software without specific prior written permission. 14*d6d9fbe2Sthorpej * 15*d6d9fbe2Sthorpej * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*d6d9fbe2Sthorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*d6d9fbe2Sthorpej * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*d6d9fbe2Sthorpej * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*d6d9fbe2Sthorpej * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*d6d9fbe2Sthorpej * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*d6d9fbe2Sthorpej * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*d6d9fbe2Sthorpej * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*d6d9fbe2Sthorpej * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*d6d9fbe2Sthorpej * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*d6d9fbe2Sthorpej * SUCH DAMAGE. 26*d6d9fbe2Sthorpej */ 27*d6d9fbe2Sthorpej 28*d6d9fbe2Sthorpej /* 29*d6d9fbe2Sthorpej * Register definitions for the Opti 82c558 PCI-ISA bridge interrupt 30*d6d9fbe2Sthorpej * controller. 31*d6d9fbe2Sthorpej */ 32*d6d9fbe2Sthorpej 33*d6d9fbe2Sthorpej /* 34*d6d9fbe2Sthorpej * PCI IRQ Select Register 35*d6d9fbe2Sthorpej */ 36*d6d9fbe2Sthorpej 37*d6d9fbe2Sthorpej #define VIPER_CFG_PIRQ 0x40 /* PCI configuration space */ 38*d6d9fbe2Sthorpej 39*d6d9fbe2Sthorpej /* 40*d6d9fbe2Sthorpej * Trigger setting: 41*d6d9fbe2Sthorpej * 42*d6d9fbe2Sthorpej * [1:7]=>5,9,10,11,12,14,15 Edge = 0 Level = 1 43*d6d9fbe2Sthorpej */ 44*d6d9fbe2Sthorpej #define VIPER_CFG_TRIGGER_SHIFT 16 45*d6d9fbe2Sthorpej 46*d6d9fbe2Sthorpej #define VIPER_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) 47*d6d9fbe2Sthorpej 48*d6d9fbe2Sthorpej #define VIPER_PIRQ_MASK 0xde20 49*d6d9fbe2Sthorpej #define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ 50*d6d9fbe2Sthorpej ((1 << (irq)) & VIPER_PIRQ_MASK) != 0) 51*d6d9fbe2Sthorpej 52*d6d9fbe2Sthorpej #define VIPER_PIRQ_NONE 0 53*d6d9fbe2Sthorpej #define VIPER_PIRQ_5 1 54*d6d9fbe2Sthorpej #define VIPER_PIRQ_9 2 55*d6d9fbe2Sthorpej #define VIPER_PIRQ_10 3 56*d6d9fbe2Sthorpej #define VIPER_PIRQ_11 4 57*d6d9fbe2Sthorpej #define VIPER_PIRQ_12 5 58*d6d9fbe2Sthorpej #define VIPER_PIRQ_14 6 59*d6d9fbe2Sthorpej #define VIPER_PIRQ_15 7 60*d6d9fbe2Sthorpej 61*d6d9fbe2Sthorpej #define VIPER_PIRQ_SELECT_MASK 0x07 62*d6d9fbe2Sthorpej #define VIPER_PIRQ_SELECT_SHIFT 3 63*d6d9fbe2Sthorpej 64*d6d9fbe2Sthorpej #define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \ 65*d6d9fbe2Sthorpej & VIPER_PIRQ_SELECT_MASK) 66