xref: /netbsd-src/sys/arch/hppa/spmath/impyu.S (revision 95e1ffb15694e54f29f8baaa4232152b703c2a5a)
1*95e1ffb1Schristos/*	$NetBSD: impyu.S,v 1.3 2005/12/11 12:17:40 christos Exp $	*/
2f4f0d8a3Sfredette
3f4f0d8a3Sfredette/*	$OpenBSD: impyu.S,v 1.5 2001/03/29 03:58:18 mickey Exp $	*/
4f4f0d8a3Sfredette
5f4f0d8a3Sfredette/*
6f4f0d8a3Sfredette * Copyright 1996 1995 by Open Software Foundation, Inc.
7f4f0d8a3Sfredette *              All Rights Reserved
8f4f0d8a3Sfredette *
9f4f0d8a3Sfredette * Permission to use, copy, modify, and distribute this software and
10f4f0d8a3Sfredette * its documentation for any purpose and without fee is hereby granted,
11f4f0d8a3Sfredette * provided that the above copyright notice appears in all copies and
12f4f0d8a3Sfredette * that both the copyright notice and this permission notice appear in
13f4f0d8a3Sfredette * supporting documentation.
14f4f0d8a3Sfredette *
15f4f0d8a3Sfredette * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
16f4f0d8a3Sfredette * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
17f4f0d8a3Sfredette * FOR A PARTICULAR PURPOSE.
18f4f0d8a3Sfredette *
19f4f0d8a3Sfredette * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
20f4f0d8a3Sfredette * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
21f4f0d8a3Sfredette * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
22f4f0d8a3Sfredette * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
23f4f0d8a3Sfredette * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24f4f0d8a3Sfredette *
25f4f0d8a3Sfredette */
26f4f0d8a3Sfredette/*
27f4f0d8a3Sfredette * pmk1.1
28f4f0d8a3Sfredette */
29f4f0d8a3Sfredette/*
30f4f0d8a3Sfredette * (c) Copyright 1986 HEWLETT-PACKARD COMPANY
31f4f0d8a3Sfredette *
32f4f0d8a3Sfredette * To anyone who acknowledges that this file is provided "AS IS"
33f4f0d8a3Sfredette * without any express or implied warranty:
34f4f0d8a3Sfredette *     permission to use, copy, modify, and distribute this file
35f4f0d8a3Sfredette * for any purpose is hereby granted without fee, provided that
36f4f0d8a3Sfredette * the above copyright notice and this notice appears in all
37f4f0d8a3Sfredette * copies, and that the name of Hewlett-Packard Company not be
38f4f0d8a3Sfredette * used in advertising or publicity pertaining to distribution
39f4f0d8a3Sfredette * of the software without specific, written prior permission.
40f4f0d8a3Sfredette * Hewlett-Packard Company makes no representations about the
41f4f0d8a3Sfredette * suitability of this software for any purpose.
42f4f0d8a3Sfredette */
43f4f0d8a3Sfredette
44f4f0d8a3Sfredette#include <machine/asm.h>
45f4f0d8a3Sfredette
46f4f0d8a3Sfredette/****************************************************************************
47f4f0d8a3Sfredette *
48f4f0d8a3Sfredette *Implement an integer multiply routine for 32-bit operands and 64-bit product
49f4f0d8a3Sfredette * with operand values of zero (multiplicand only) and 2**32reated specially.
50f4f0d8a3Sfredette * The algorithm uses the multiplier, four bits at a time, from right to left,
51f4f0d8a3Sfredette * to generate partial product.  Execution speed is more important than program
52f4f0d8a3Sfredette * size in this implementation.
53f4f0d8a3Sfredette *
54f4f0d8a3Sfredette *****************************************************************************/
55f4f0d8a3Sfredette;
56f4f0d8a3Sfredette; Definitions - General registers
57f4f0d8a3Sfredette;
5806332c88Schsgr0:	.equ		0		; General register zero
5906332c88Schspu:	.equ		3		; upper part of product
6006332c88Schspl:	.equ		4		; lower part of product
6106332c88Schsop2:	.equ		4		; multiplier
6206332c88Schsop1:	.equ		5		; multiplicand
6306332c88Schscnt:	.equ		6		; count in multiply
6406332c88Schsbrindex:.equ		7		; index into the br. table
6506332c88Schssaveop2:.equ		8		; save op2 if high bit of multiplicand
66f4f0d8a3Sfredette					; is set
6706332c88Schspc:	.equ		9		; carry bit of product, = 00...01
6806332c88Schspm:	.equ	       10		; value of -1 used in shifting
6906332c88Schstemp:	.equ		6
70f4f0d8a3Sfredette
71f4f0d8a3Sfredette;****************************************************************************
72f4f0d8a3Sfredette	.export impyu,entry
73f4f0d8a3Sfredette	.text
74f4f0d8a3Sfredette	.align 4
75f4f0d8a3Sfredette	.proc
76f4f0d8a3Sfredette	.callinfo
77f4f0d8a3Sfredette;
78f4f0d8a3Sfredette;****************************************************************************
7906332c88Schsimpyu:	stws,ma		pu,4(%sp)		; save registers on stack
8006332c88Schs	stws,ma		pl,4(%sp)		; save registers on stack
8106332c88Schs	stws,ma		op1,4(%sp)		; save registers on stack
8206332c88Schs	stws,ma		cnt,4(%sp)		; save registers on stack
8306332c88Schs	stws,ma		brindex,4(%sp)		; save registers on stack
8406332c88Schs	stws,ma		saveop2,4(%sp)		; save registers on stack
8506332c88Schs	stws,ma		pc,4(%sp)		; save registers on stack
8606332c88Schs	stws,ma		pm,4(%sp)		; save registers on stack
87f4f0d8a3Sfredette;
88f4f0d8a3Sfredette;   Start multiply process
89f4f0d8a3Sfredette;
9006332c88Schs	ldws		0(%arg0),op1		; get multiplicand
9106332c88Schs	ldws		0(%arg1),op2		; get multiplier
92f4f0d8a3Sfredette	addib,=		0,op1,fini0		; op1 = 0, product = 0
93f4f0d8a3Sfredette	addi		0,gr0,pu		; clear product
94f4f0d8a3Sfredette	bb,>=		op1,0,mpy1		; test msb of multiplicand
95f4f0d8a3Sfredette	addi		0,gr0,saveop2		; clear saveop2
96f4f0d8a3Sfredette;
97f4f0d8a3Sfredette; msb of multiplicand is set so will save multiplier for a final
98f4f0d8a3Sfredette; addition into the result
99f4f0d8a3Sfredette;
100f4f0d8a3Sfredette	extru,=		op1,31,31,op1		; clear msb of multiplicand
101f4f0d8a3Sfredette	b		mpy1			; if op1 < 2**32, start multiply
102f4f0d8a3Sfredette	add		op2,gr0,saveop2		;   save op2 in saveop2
103f4f0d8a3Sfredette	shd		gr0,op2,1,pu		; shift op2 left 31 for result
104f4f0d8a3Sfredette	b		fini			; go to finish
105f4f0d8a3Sfredette	shd		op2,gr0,1,pl
106f4f0d8a3Sfredette;
10706332c88Schsmpy1:	addi		-1,gr0,pm		; initialize pm to 111...1
108f4f0d8a3Sfredette	addi		1,gr0,pc		; initialize pc to 00...01
109f4f0d8a3Sfredette	movib,tr	8,cnt,mloop		; set count for mpy loop
110f4f0d8a3Sfredette	extru		op2,31,4,brindex	; 4 bits as index into table
111f4f0d8a3Sfredette;
112f4f0d8a3Sfredette	.align		8
113f4f0d8a3Sfredette;
114f4f0d8a3Sfredette	b		sh4c			; br. if sign overflow
11506332c88Schssh4n:	shd		pu,pl,4,pl		; shift product right 4 bits
116f4f0d8a3Sfredette	addib,<=	-1,cnt,mulend		; reduce count by 1, exit if
117f4f0d8a3Sfredette	extru		pu,27,28,pu		;   <= zero
118f4f0d8a3Sfredette;
11906332c88Schsmloop:	blr		brindex,gr0		; br. into table
120f4f0d8a3Sfredette						;   entries of 2 words
121f4f0d8a3Sfredette	extru		op2,27,4,brindex	; next 4 bits into index
122f4f0d8a3Sfredette;
123f4f0d8a3Sfredette;
124f4f0d8a3Sfredette;	branch table for the multiplication process with four multiplier bits
125f4f0d8a3Sfredette;
12606332c88Schsmtable:						; two words per entry
127f4f0d8a3Sfredette;
128f4f0d8a3Sfredette; ----	bits = 0000 ---- shift product 4 bits -------------------------------
129f4f0d8a3Sfredette;
130f4f0d8a3Sfredette	b		sh4n+4			; just shift partial
131f4f0d8a3Sfredette	shd		pu,pl,4,pl		;   product right 4 bits
132f4f0d8a3Sfredette;
133f4f0d8a3Sfredette;  ----	bits = 0001 ---- add op1, then shift 4 bits
134f4f0d8a3Sfredette;
135f4f0d8a3Sfredette	addb,tr		op1,pu,sh4n+4		; add op1 to product, to shift
136f4f0d8a3Sfredette	shd		pu,pl,4,pl		;   product right 4 bits
137f4f0d8a3Sfredette;
138f4f0d8a3Sfredette;  ----	bits = 0010 ---- add op1, add op1, then shift 4 bits
139f4f0d8a3Sfredette;
140f4f0d8a3Sfredette	addb,tr		op1,pu,sh4n		; add 2*op1, to shift
141f4f0d8a3Sfredette	addb,uv		op1,pu,sh4c		;   product right 4 bits
142f4f0d8a3Sfredette;
143f4f0d8a3Sfredette;  ---- bits = 0011 ---- add op1, add 2*op1, shift 4 bits
144f4f0d8a3Sfredette;
145f4f0d8a3Sfredette	addb,tr		op1,pu,sh4n-4		; add op1 & 2*op1, shift
146f4f0d8a3Sfredette	sh1add,nuv	op1,pu,pu		;   product right 4 bits
147f4f0d8a3Sfredette;
148f4f0d8a3Sfredette;  ----	bits = 0100 ---- shift 2, add op1, shift 2
149f4f0d8a3Sfredette;
150f4f0d8a3Sfredette	b		sh2sa
151f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift product 2 bits
152f4f0d8a3Sfredette;
153f4f0d8a3Sfredette;  ----	bits = 0101 ---- add op1, shift 2, add op1, and shift 2 again
154f4f0d8a3Sfredette;
155f4f0d8a3Sfredette	addb,tr		op1,pu,sh2us		; add op1 to product
156f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift 2 bits
157f4f0d8a3Sfredette;
158f4f0d8a3Sfredette;  ----	bits = 0110 ---- add op1, add op1, shift 2, add op1, and shift 2 again
159f4f0d8a3Sfredette;
160f4f0d8a3Sfredette	addb,tr		op1,pu,sh2c		; add 2*op1, to shift 2 bits
161f4f0d8a3Sfredette	addb,nuv	op1,pu,sh2us		; br. if not overflow
162f4f0d8a3Sfredette;
163f4f0d8a3Sfredette;  ----	bits = 0111 ---- subtract op1, shift 3, add op1, and shift 1
164f4f0d8a3Sfredette;
165f4f0d8a3Sfredette	b		sh3s
166f4f0d8a3Sfredette	sub		pu,op1,pu		; subtract op1, br. to sh3s
167f4f0d8a3Sfredette
168f4f0d8a3Sfredette;
169f4f0d8a3Sfredette;  ----	bits = 1000 ---- shift 3, add op1, shift 1
170f4f0d8a3Sfredette;
171f4f0d8a3Sfredette	b		sh3sa
172f4f0d8a3Sfredette	shd		pu,pl,3,pl		; shift product right 3 bits
173f4f0d8a3Sfredette;
174f4f0d8a3Sfredette;  ----	bits = 1001 ---- add op1, shift 3, add op1, shift 1
175f4f0d8a3Sfredette;
176f4f0d8a3Sfredette	addb,tr		op1,pu,sh3us		; add op1, to shift 3, add op1,
177f4f0d8a3Sfredette	shd		pu,pl,3,pl		;   and shift 1
178f4f0d8a3Sfredette;
179f4f0d8a3Sfredette;  ----	bits = 1010 ---- add op1, add op1, shift 3, add op1, shift 1
180f4f0d8a3Sfredette;
181f4f0d8a3Sfredette	addb,tr		op1,pu,sh3c		; add 2*op1, to shift 3 bits
182f4f0d8a3Sfredette	addb,nuv	op1,pu,sh3us		;   br. if no overflow
183f4f0d8a3Sfredette;
184f4f0d8a3Sfredette;  ----	bits = 1011 ---- add -op1, shift 2, add -op1, shift 2, inc. next index
185f4f0d8a3Sfredette;
186f4f0d8a3Sfredette	addib,tr	1,brindex,sh2s		; add 1 to index, subtract op1,
187f4f0d8a3Sfredette	sub		pu,op1,pu		;   shift 2 with minus sign
188f4f0d8a3Sfredette;
189f4f0d8a3Sfredette;  ----	bits = 1100 ---- shift 2, subtract op1, shift 2, increment next index
190f4f0d8a3Sfredette;
191f4f0d8a3Sfredette	addib,tr	1,brindex,sh2sb		; add 1 to index, to shift
192f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift right 2 bits signed
193f4f0d8a3Sfredette;
194f4f0d8a3Sfredette;  ----	bits = 1101 ---- add op1, shift 2, add -op1, shift 2
195f4f0d8a3Sfredette;
196f4f0d8a3Sfredette	addb,tr		op1,pu,sh2ns		; add op1, to shift 2
197f4f0d8a3Sfredette	shd		pu,pl,2,pl		;   right 2 unsigned, etc.
198f4f0d8a3Sfredette;
199f4f0d8a3Sfredette;  ----	bits = 1110 ---- shift 1 signed, add -op1, shift 3 signed
200f4f0d8a3Sfredette;
201f4f0d8a3Sfredette	addib,tr	1,brindex,sh1sa		; add 1 to index, to shift
202f4f0d8a3Sfredette	shd		pu,pl,1,pl		; shift 1 bit
203f4f0d8a3Sfredette;
204f4f0d8a3Sfredette;  ----	bits = 1111 ---- add -op1, shift 4 signed
205f4f0d8a3Sfredette;
206f4f0d8a3Sfredette	addib,tr	1,brindex,sh4s		; add 1 to index, subtract op1,
207f4f0d8a3Sfredette	sub		pu,op1,pu		;   to shift 4 signed
208f4f0d8a3Sfredette
209f4f0d8a3Sfredette;
210f4f0d8a3Sfredette;  ----	bits = 10000 ---- shift 4 signed
211f4f0d8a3Sfredette;
212f4f0d8a3Sfredette	addib,tr	1,brindex,sh4s+4	; add 1 to index
213f4f0d8a3Sfredette	shd		pu,pl,4,pl		; shift 4 signed
214f4f0d8a3Sfredette;
215f4f0d8a3Sfredette;  ---- end of table ---------------------------------------------------------
216f4f0d8a3Sfredette;
21706332c88Schssh4s:	shd		pu,pl,4,pl
218f4f0d8a3Sfredette	addib,>		-1,cnt,mloop		; decrement count, loop if > 0
219f4f0d8a3Sfredette	shd		pm,pu,4,pu		; shift 4, minus signed
220f4f0d8a3Sfredette	addb,tr		op1,pu,lastadd		; do one more add, then finish
221f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
222f4f0d8a3Sfredette;
22306332c88Schssh4c:	addib,>		-1,cnt,mloop		; decrement count, loop if > 0
224f4f0d8a3Sfredette	shd		pc,pu,4,pu		; shift 4 with overflow
225f4f0d8a3Sfredette	b		lastadd			; end of multiply
226f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
227f4f0d8a3Sfredette;
22806332c88Schssh3c:	shd		pu,pl,3,pl		; shift product 3 bits
229f4f0d8a3Sfredette	shd		pc,pu,3,pu		; shift 3 signed
230f4f0d8a3Sfredette	addb,tr		op1,pu,sh1		; add op1, to shift 1 bit
231f4f0d8a3Sfredette	shd		pu,pl,1,pl
232f4f0d8a3Sfredette;
23306332c88Schssh3us:	extru		pu,28,29,pu		; shift 3 unsigned
234f4f0d8a3Sfredette	addb,tr		op1,pu,sh1		; add op1, to shift 1 bit
235f4f0d8a3Sfredette	shd		pu,pl,1,pl
236f4f0d8a3Sfredette;
23706332c88Schssh3sa:	extrs		pu,28,29,pu		; shift 3 signed
238f4f0d8a3Sfredette	addb,tr		op1,pu,sh1		; add op1, to shift 1 bit
239f4f0d8a3Sfredette	shd		pu,pl,1,pl
240f4f0d8a3Sfredette;
24106332c88Schssh3s:	shd		pu,pl,3,pl		; shift 3 minus signed
242f4f0d8a3Sfredette	shd		pm,pu,3,pu
243f4f0d8a3Sfredette	addb,tr		op1,pu,sh1		; add op1, to shift 1 bit
244f4f0d8a3Sfredette	shd		pu,pl,1,pl
245f4f0d8a3Sfredette;
24606332c88Schssh1:	addib,>		-1,cnt,mloop		; loop if count > 0
247f4f0d8a3Sfredette	extru		pu,30,31,pu
248f4f0d8a3Sfredette	b		lastadd			; end of multiply
249f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
250f4f0d8a3Sfredette;
25106332c88Schssh2ns:	addib,tr	1,brindex,sh2sb+4	; increment index
252f4f0d8a3Sfredette	extru		pu,29,30,pu		; shift unsigned
253f4f0d8a3Sfredette;
25406332c88Schssh2s:	shd		pu,pl,2,pl		; shift with minus sign
255f4f0d8a3Sfredette	shd		pm,pu,2,pu		;
256f4f0d8a3Sfredette	sub		pu,op1,pu		; subtract op1
257f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift with minus sign
258f4f0d8a3Sfredette	addib,>		-1,cnt,mloop		; decrement count, loop if > 0
259f4f0d8a3Sfredette	shd		pm,pu,2,pu		; shift with minus sign
260f4f0d8a3Sfredette	addb,tr		op1,pu,lastadd		; do one more add, then finish
261f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
262f4f0d8a3Sfredette;
26306332c88Schssh2sb:	extrs		pu,29,30,pu		; shift 2 signed
264f4f0d8a3Sfredette	sub		pu,op1,pu		; subtract op1 from product
265f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift with minus sign
266f4f0d8a3Sfredette	addib,>		-1,cnt,mloop		; decrement count, loop if > 0
267f4f0d8a3Sfredette	shd		pm,pu,2,pu		; shift with minus sign
268f4f0d8a3Sfredette	addb,tr		op1,pu,lastadd		; do one more add, then finish
269f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
270f4f0d8a3Sfredette;
27106332c88Schssh1sa:	extrs		pu,30,31,pu		;   signed
272f4f0d8a3Sfredette	sub		pu,op1,pu		; subtract op1 from product
273f4f0d8a3Sfredette	shd		pu,pl,3,pl		; shift 3 with minus sign
274f4f0d8a3Sfredette	addib,>		-1,cnt,mloop		; decrement count, loop if >0
275f4f0d8a3Sfredette	shd		pm,pu,3,pu
276f4f0d8a3Sfredette	addb,tr		op1,pu,lastadd		; do one more add, then finish
277f4f0d8a3Sfredette	addb,=,n	saveop2,gr0,fini	; check saveop2
278f4f0d8a3Sfredette;
27906332c88Schsfini0:	movib,tr	0,pl,fini		; product = 0 as op1 = 0
28006332c88Schs	stws		pu,0(%arg2)		; save high part of result
281f4f0d8a3Sfredette;
28206332c88Schssh2us:	extru		pu,29,30,pu		; shift 2 unsigned
283f4f0d8a3Sfredette	addb,tr		op1,pu,sh2a		; add op1
284f4f0d8a3Sfredette	shd		pu,pl,2,pl		; shift 2 bits
285f4f0d8a3Sfredette;
28606332c88Schssh2c:	shd		pu,pl,2,pl
287f4f0d8a3Sfredette	shd		pc,pu,2,pu		; shift with carry
288f4f0d8a3Sfredette	addb,tr		op1,pu,sh2a		; add op1 to product
289f4f0d8a3Sfredette	shd		pu,pl,2,pl		; br. to sh2 to shift pu
290f4f0d8a3Sfredette;
29106332c88Schssh2sa:	extrs		pu,29,30,pu		; shift with sign
292f4f0d8a3Sfredette	addb,tr		op1,pu,sh2a		; add op1 to product
293f4f0d8a3Sfredette	shd		pu,pl,2,pl		; br. to sh2 to shift pu
294f4f0d8a3Sfredette;
29506332c88Schssh2a:	addib,>		-1,cnt,mloop		; loop if count > 0
296f4f0d8a3Sfredette	extru		pu,29,30,pu
297f4f0d8a3Sfredette;
29806332c88Schsmulend:	addb,=,n	saveop2,gr0,fini	; check saveop2
29906332c88Schslastadd:shd		saveop2,gr0,1,temp	;  if saveop2 <> 0, shift it
300f4f0d8a3Sfredette	shd		gr0,saveop2,1,saveop2	;  left 31 and add to result
301f4f0d8a3Sfredette	add		pl,temp,pl
302f4f0d8a3Sfredette	addc		pu,saveop2,pu
303f4f0d8a3Sfredette;
304f4f0d8a3Sfredette;	finish
305f4f0d8a3Sfredette;
30606332c88Schsfini:	stws		pu,0(%arg2)		; save high part of result
30706332c88Schs	stws		pl,4(%arg2)		; save low part of result
308f4f0d8a3Sfredette
30906332c88Schs	ldws,mb		-4(%sp),pm		; restore registers
31006332c88Schs	ldws,mb		-4(%sp),pc		; restore registers
31106332c88Schs	ldws,mb		-4(%sp),saveop2		; restore registers
31206332c88Schs	ldws,mb		-4(%sp),brindex		; restore registers
31306332c88Schs	ldws,mb		-4(%sp),cnt		; restore registers
31406332c88Schs	ldws,mb		-4(%sp),op1		; restore registers
31506332c88Schs	ldws,mb		-4(%sp),pl		; restore registers
31606332c88Schs	bv		0(%rp)			; return
31706332c88Schs	ldws,mb		-4(%sp),pu		; restore registers
318f4f0d8a3Sfredette
319f4f0d8a3Sfredette	.procend
320f4f0d8a3Sfredette	.end
321