xref: /netbsd-src/sys/arch/hppa/dev/dino.c (revision dbeed5211bb070f13a01c576c13ceba139116a04)
1*dbeed521Smacallan /*	$NetBSD: dino.c,v 1.17 2024/01/28 09:03:22 macallan Exp $ */
26d3ceb1dSskrll 
36d3ceb1dSskrll /*	$OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $	*/
46d3ceb1dSskrll 
56d3ceb1dSskrll /*
66d3ceb1dSskrll  * Copyright (c) 2003 Michael Shalayeff
76d3ceb1dSskrll  * All rights reserved.
86d3ceb1dSskrll  *
96d3ceb1dSskrll  * Redistribution and use in source and binary forms, with or without
106d3ceb1dSskrll  * modification, are permitted provided that the following conditions
116d3ceb1dSskrll  * are met:
126d3ceb1dSskrll  * 1. Redistributions of source code must retain the above copyright
136d3ceb1dSskrll  *    notice, this list of conditions and the following disclaimer.
146d3ceb1dSskrll  * 2. Redistributions in binary form must reproduce the above copyright
156d3ceb1dSskrll  *    notice, this list of conditions and the following disclaimer in the
166d3ceb1dSskrll  *    documentation and/or other materials provided with the distribution.
176d3ceb1dSskrll  *
186d3ceb1dSskrll  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
196d3ceb1dSskrll  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
206d3ceb1dSskrll  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
216d3ceb1dSskrll  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
226d3ceb1dSskrll  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
236d3ceb1dSskrll  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
246d3ceb1dSskrll  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
256d3ceb1dSskrll  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
266d3ceb1dSskrll  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
276d3ceb1dSskrll  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
286d3ceb1dSskrll  * THE POSSIBILITY OF SUCH DAMAGE.
296d3ceb1dSskrll  */
306d3ceb1dSskrll 
316d3ceb1dSskrll #include <sys/cdefs.h>
32*dbeed521Smacallan __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.17 2024/01/28 09:03:22 macallan Exp $");
336d3ceb1dSskrll 
346d3ceb1dSskrll /* #include "cardbus.h" */
356d3ceb1dSskrll 
366d3ceb1dSskrll #include <sys/param.h>
376d3ceb1dSskrll #include <sys/systm.h>
386d3ceb1dSskrll #include <sys/device.h>
396d3ceb1dSskrll #include <sys/reboot.h>
406d3ceb1dSskrll #include <sys/extent.h>
416d3ceb1dSskrll 
426d3ceb1dSskrll #include <machine/iomod.h>
436d3ceb1dSskrll #include <machine/autoconf.h>
446d3ceb1dSskrll #include <machine/intr.h>
456d3ceb1dSskrll 
466d3ceb1dSskrll #include <hppa/include/vmparam.h>
476d3ceb1dSskrll #include <hppa/dev/cpudevs.h>
486d3ceb1dSskrll 
496d3ceb1dSskrll #if NCARDBUS > 0
506d3ceb1dSskrll #include <dev/cardbus/rbus.h>
516d3ceb1dSskrll #endif
526d3ceb1dSskrll 
536d3ceb1dSskrll #include <dev/pci/pcireg.h>
546d3ceb1dSskrll #include <dev/pci/pcivar.h>
556d3ceb1dSskrll #include <dev/pci/pcidevs.h>
566d3ceb1dSskrll 
576d3ceb1dSskrll #define	DINO_MEM_CHUNK	0x800000
586d3ceb1dSskrll 
596d3ceb1dSskrll /* from machdep.c */
606d3ceb1dSskrll extern struct extent *hppa_io_extent;
616d3ceb1dSskrll 
626d3ceb1dSskrll struct dino_regs {
636d3ceb1dSskrll 	/* HPA Supervisory Register Set */
646d3ceb1dSskrll 	uint32_t	pad0;		/* 0x000 */
656d3ceb1dSskrll 	uint32_t	iar0;		/* 0x004 rw intr addr reg 0 */
666d3ceb1dSskrll 	uint32_t	iodc;		/* 0x008 rw iodc data/addr */
676d3ceb1dSskrll 	uint32_t	irr0;		/* 0x00c r  intr req reg 0 */
686d3ceb1dSskrll 	uint32_t	iar1;		/* 0x010 rw intr addr reg 1 */
696d3ceb1dSskrll 	uint32_t	irr1;		/* 0x014 r  intr req reg 1 */
706d3ceb1dSskrll 	uint32_t	imr;		/* 0x018 rw intr mask reg */
716d3ceb1dSskrll 	uint32_t	ipr;		/* 0x01c rw intr pending reg */
726d3ceb1dSskrll 	uint32_t	toc_addr;	/* 0x020 rw TOC addr reg */
736d3ceb1dSskrll 	uint32_t	icr;		/* 0x024 rw intr control reg */
746d3ceb1dSskrll 	uint32_t	ilr;		/* 0x028 r  intr level reg */
756d3ceb1dSskrll 	uint32_t	pad1;		/* 0x02c */
766d3ceb1dSskrll 	uint32_t	io_command;	/* 0x030  w command register */
776d3ceb1dSskrll 	uint32_t	io_status;	/* 0x034 r  status register */
786d3ceb1dSskrll 	uint32_t	io_control;	/* 0x038 rw control register */
796d3ceb1dSskrll 	uint32_t	pad2;		/* 0x03c AUX registers follow */
806d3ceb1dSskrll 
816d3ceb1dSskrll 	/* HPA Auxiliary Register Set */
826d3ceb1dSskrll 	uint32_t	io_gsc_err_addr;/* 0x040 GSC error address */
836d3ceb1dSskrll 	uint32_t	io_err_info;	/* 0x044 error info register */
846d3ceb1dSskrll 	uint32_t	io_pci_err_addr;/* 0x048 PCI error address */
856d3ceb1dSskrll 	uint32_t	pad3[4];	/* 0x04c */
866d3ceb1dSskrll 	uint32_t	io_fbb_en;	/* 0x05c fast back2back enable reg */
876d3ceb1dSskrll 	uint32_t	io_addr_en;	/* 0x060 address enable reg */
886d3ceb1dSskrll 	uint32_t	pci_addr;	/* 0x064 PCI conf/io/mem addr reg */
896d3ceb1dSskrll 	uint32_t	pci_conf_data;	/* 0x068 PCI conf data reg */
906d3ceb1dSskrll 	uint32_t	pci_io_data;	/* 0x06c PCI io data reg */
916d3ceb1dSskrll 	uint32_t	pci_mem_data;	/* 0x070 PCI memory data reg */
926d3ceb1dSskrll 	uint32_t	pad4[0x740/4];	/* 0x074 */
936d3ceb1dSskrll 
946d3ceb1dSskrll 	/* HPA Bus (GSC) Specific-Dependent Register Set */
956d3ceb1dSskrll 	uint32_t	gsc2x_config;	/* 0x7b4 GSC2X config reg */
966d3ceb1dSskrll 	uint32_t	pad5[0x48/4];	/* 0x7b8: BSRS registers follow */
976d3ceb1dSskrll 
986d3ceb1dSskrll 	/* HPA HVERSION (Dino)-Dependent Register Set */
996d3ceb1dSskrll 	uint32_t	gmask;		/* 0x800 GSC arbitration mask */
1006d3ceb1dSskrll 	uint32_t	pamr;		/* 0x804 PCI arbitration mask */
1016d3ceb1dSskrll 	uint32_t	papr;		/* 0x808 PCI arbitration priority */
1026d3ceb1dSskrll 	uint32_t	damode;		/* 0x80c PCI arbitration mode */
1036d3ceb1dSskrll 	uint32_t	pcicmd;		/* 0x810 PCI command register */
1046d3ceb1dSskrll 	uint32_t	pcists;		/* 0x814 PCI status register */
1056d3ceb1dSskrll 	uint32_t	pad6;		/* 0x818 */
1066d3ceb1dSskrll 	uint32_t	mltim;		/* 0x81c PCI master latency timer */
1076d3ceb1dSskrll 	uint32_t	brdg_feat;	/* 0x820 PCI bridge feature enable */
1086d3ceb1dSskrll 	uint32_t	pciror;		/* 0x824 PCI read optimization reg */
1096d3ceb1dSskrll 	uint32_t	pciwor;		/* 0x828 PCI write optimization reg */
1106d3ceb1dSskrll 	uint32_t	pad7;		/* 0x82c */
1116d3ceb1dSskrll 	uint32_t	tltim;		/* 0x830 PCI target latency reg */
1126d3ceb1dSskrll };
1136d3ceb1dSskrll 
1146d3ceb1dSskrll struct dino_softc {
1156d3ceb1dSskrll 	device_t sc_dv;
1166d3ceb1dSskrll 
1176d3ceb1dSskrll 	int sc_ver;
1186d3ceb1dSskrll 	void *sc_ih;
1196d3ceb1dSskrll 	struct hppa_interrupt_register sc_ir;
1206d3ceb1dSskrll 	bus_space_tag_t sc_bt;
1216d3ceb1dSskrll 	bus_space_handle_t sc_bh;
1226d3ceb1dSskrll 	bus_dma_tag_t sc_dmat;
123a7203f53Sskrll 
124a7203f53Sskrll 	struct hppa_bus_dma_tag sc_dmatag;
125a7203f53Sskrll 	struct hppa_bus_space_tag sc_memt;
126a7203f53Sskrll 
1276d3ceb1dSskrll 	volatile struct dino_regs *sc_regs;
1286d3ceb1dSskrll 
1296d3ceb1dSskrll 	struct hppa_pci_chipset_tag sc_pc;
1306d3ceb1dSskrll 	struct hppa_bus_space_tag sc_iot;
131a7203f53Sskrll 
1326d3ceb1dSskrll 	struct extent *sc_ioex;
1336d3ceb1dSskrll 	int sc_memrefcount[30];
134a7203f53Sskrll 
135a7203f53Sskrll 	char sc_ioexname[20];
1366d3ceb1dSskrll };
1376d3ceb1dSskrll 
1386d3ceb1dSskrll int	dinomatch(device_t, struct cfdata *, void *);
1396d3ceb1dSskrll void	dinoattach(device_t, device_t, void *);
1406d3ceb1dSskrll static device_t	dino_callback(device_t, struct confargs *);
1416d3ceb1dSskrll 
1426d3ceb1dSskrll CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL,
1436d3ceb1dSskrll     NULL);
1446d3ceb1dSskrll 
1456d3ceb1dSskrll void dino_attach_hook(device_t, device_t,
1466d3ceb1dSskrll     struct pcibus_attach_args *);
1476d3ceb1dSskrll void dino_enable_bus(struct dino_softc *, int);
1486d3ceb1dSskrll int dino_maxdevs(void *, int);
1496d3ceb1dSskrll pcitag_t dino_make_tag(void *, int, int, int);
1506d3ceb1dSskrll void dino_decompose_tag(void *, pcitag_t, int *, int *, int *);
1516d3ceb1dSskrll pcireg_t dino_conf_read(void *, pcitag_t, int);
1526d3ceb1dSskrll void dino_conf_write(void *, pcitag_t, int, pcireg_t);
1536d3ceb1dSskrll 
1546d3ceb1dSskrll int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
15526c6de43Schristos const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t);
1566d3ceb1dSskrll void *dino_intr_establish(void *, pci_intr_handle_t, int,
1576d3ceb1dSskrll     int (*)(void *), void *);
1586d3ceb1dSskrll void dino_intr_disestablish(void *, void *);
1596d3ceb1dSskrll 
1606d3ceb1dSskrll void *dino_alloc_parent(device_t, struct pci_attach_args *, int);
1616d3ceb1dSskrll 
1626d3ceb1dSskrll int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
1636d3ceb1dSskrll int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
1646d3ceb1dSskrll int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t,
1656d3ceb1dSskrll     bus_space_handle_t *);
1666d3ceb1dSskrll int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t,
1676d3ceb1dSskrll     bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
1686d3ceb1dSskrll int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t,
1696d3ceb1dSskrll     bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
1706d3ceb1dSskrll void dino_unmap(void *, bus_space_handle_t, bus_size_t);
1716d3ceb1dSskrll void dino_free(void *, bus_space_handle_t, bus_size_t);
1726d3ceb1dSskrll void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int);
1736d3ceb1dSskrll void *dino_vaddr(void *, bus_space_handle_t);
1746d3ceb1dSskrll paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int);
1756d3ceb1dSskrll 
1766d3ceb1dSskrll uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t);
1776d3ceb1dSskrll uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t);
1786d3ceb1dSskrll uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t);
1796d3ceb1dSskrll uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t);
180*dbeed521Smacallan uint16_t dino_rs2(void *, bus_space_handle_t, bus_size_t);
181*dbeed521Smacallan uint32_t dino_rs4(void *, bus_space_handle_t, bus_size_t);
182*dbeed521Smacallan uint64_t dino_rs8(void *, bus_space_handle_t, bus_size_t);
1836d3ceb1dSskrll void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t);
1846d3ceb1dSskrll void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t);
1856d3ceb1dSskrll void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t);
1866d3ceb1dSskrll void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t);
187*dbeed521Smacallan void dino_ws2(void *, bus_space_handle_t, bus_size_t, uint16_t);
188*dbeed521Smacallan void dino_ws4(void *, bus_space_handle_t, bus_size_t, uint32_t);
189*dbeed521Smacallan void dino_ws8(void *, bus_space_handle_t, bus_size_t, uint64_t);
1906d3ceb1dSskrll void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
1916d3ceb1dSskrll void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
1926d3ceb1dSskrll void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
1936d3ceb1dSskrll void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
1946d3ceb1dSskrll void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
1956d3ceb1dSskrll     bus_size_t);
1966d3ceb1dSskrll void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
1976d3ceb1dSskrll     bus_size_t);
1986d3ceb1dSskrll void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
1996d3ceb1dSskrll     bus_size_t);
2006d3ceb1dSskrll void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
2016d3ceb1dSskrll     bus_size_t);
2026d3ceb1dSskrll void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
2036d3ceb1dSskrll void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
2046d3ceb1dSskrll void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
2056d3ceb1dSskrll void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
2066d3ceb1dSskrll void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
2076d3ceb1dSskrll     bus_size_t);
2086d3ceb1dSskrll void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
2096d3ceb1dSskrll     bus_size_t);
2106d3ceb1dSskrll void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
2116d3ceb1dSskrll     bus_size_t);
2126d3ceb1dSskrll void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
2136d3ceb1dSskrll     bus_size_t);
2146d3ceb1dSskrll void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
2156d3ceb1dSskrll     bus_size_t);
2166d3ceb1dSskrll void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
2176d3ceb1dSskrll     bus_size_t);
2186d3ceb1dSskrll void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t);
2196d3ceb1dSskrll void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t);
2206d3ceb1dSskrll void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t);
2216d3ceb1dSskrll void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t);
2226d3ceb1dSskrll void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
2236d3ceb1dSskrll     bus_size_t);
2246d3ceb1dSskrll void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
2256d3ceb1dSskrll     bus_size_t);
2266d3ceb1dSskrll void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
2276d3ceb1dSskrll     bus_size_t);
2286d3ceb1dSskrll void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
2296d3ceb1dSskrll     bus_size_t);
2306d3ceb1dSskrll void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
2316d3ceb1dSskrll     bus_size_t);
2326d3ceb1dSskrll void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
2336d3ceb1dSskrll     bus_size_t);
2346d3ceb1dSskrll void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
2356d3ceb1dSskrll     bus_size_t);
2366d3ceb1dSskrll void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
2376d3ceb1dSskrll     bus_size_t);
2386d3ceb1dSskrll void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
2396d3ceb1dSskrll     bus_size_t);
2406d3ceb1dSskrll void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
2416d3ceb1dSskrll     bus_size_t);
2426d3ceb1dSskrll void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t);
2436d3ceb1dSskrll void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t);
2446d3ceb1dSskrll void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t);
2456d3ceb1dSskrll void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t);
2466d3ceb1dSskrll void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
2476d3ceb1dSskrll     bus_size_t, bus_size_t);
2486d3ceb1dSskrll void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
2496d3ceb1dSskrll     bus_size_t, bus_size_t);
2506d3ceb1dSskrll void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
2516d3ceb1dSskrll     bus_size_t, bus_size_t);
2526d3ceb1dSskrll void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t,
2536d3ceb1dSskrll     bus_size_t, bus_size_t);
2546d3ceb1dSskrll int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int,
2556d3ceb1dSskrll     bus_dmamap_t *);
2566d3ceb1dSskrll void dino_dmamap_destroy(void *, bus_dmamap_t);
2576d3ceb1dSskrll int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *,
2586d3ceb1dSskrll     int);
2596d3ceb1dSskrll int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int);
2606d3ceb1dSskrll int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int);
2616d3ceb1dSskrll int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int,
2626d3ceb1dSskrll     bus_size_t, int);
2636d3ceb1dSskrll void dino_dmamap_unload(void *, bus_dmamap_t);
2646d3ceb1dSskrll void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int);
2656d3ceb1dSskrll int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t,
2666d3ceb1dSskrll     bus_dma_segment_t *, int, int *, int);
2676d3ceb1dSskrll void dino_dmamem_free(void *, bus_dma_segment_t *, int);
2686d3ceb1dSskrll int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int);
2696d3ceb1dSskrll void dino_dmamem_unmap(void *, void *, size_t);
2706d3ceb1dSskrll paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int);
2716d3ceb1dSskrll 
2726d3ceb1dSskrll 
2736d3ceb1dSskrll void
dino_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)2746d3ceb1dSskrll dino_attach_hook(device_t parent, device_t self,
2756d3ceb1dSskrll     struct pcibus_attach_args *pba)
2766d3ceb1dSskrll {
2776d3ceb1dSskrll 	struct dino_softc *sc = pba->pba_pc->_cookie;
2786d3ceb1dSskrll 
2796d3ceb1dSskrll 	/*
2806d3ceb1dSskrll 	 * The firmware enables only devices that are needed for booting.
2816d3ceb1dSskrll 	 * So other devices will fail to map PCI MEM / IO when they attach.
2826d3ceb1dSskrll 	 * Therefore we recursively walk all buses to simply enable everything.
2836d3ceb1dSskrll 	 */
2846d3ceb1dSskrll 	dino_enable_bus(sc, 0);
2856d3ceb1dSskrll }
2866d3ceb1dSskrll 
2876d3ceb1dSskrll void
dino_enable_bus(struct dino_softc * sc,int bus)2886d3ceb1dSskrll dino_enable_bus(struct dino_softc *sc, int bus)
2896d3ceb1dSskrll {
2906d3ceb1dSskrll 	int func;
2916d3ceb1dSskrll 	int dev;
2926d3ceb1dSskrll 	pcitag_t tag;
2936d3ceb1dSskrll 	pcireg_t data;
2946d3ceb1dSskrll 	pcireg_t class;
2956d3ceb1dSskrll 
2966d3ceb1dSskrll 	for (dev = 0; dev < 32; dev++) {
2976d3ceb1dSskrll 		tag = dino_make_tag(sc, bus, dev, 0);
2986d3ceb1dSskrll 		if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) {
2996d3ceb1dSskrll 			for (func = 0; func < 8; func++) {
3006d3ceb1dSskrll 				tag = dino_make_tag(sc, bus, dev, func);
3016d3ceb1dSskrll 				if (dino_conf_read(sc, tag, 0) != 0xffffffff) {
3026d3ceb1dSskrll 					data = dino_conf_read(sc, tag,
3036d3ceb1dSskrll 					    PCI_COMMAND_STATUS_REG);
3046d3ceb1dSskrll 					dino_conf_write(sc, tag,
3056d3ceb1dSskrll 					    PCI_COMMAND_STATUS_REG,
3066d3ceb1dSskrll 					    PCI_COMMAND_IO_ENABLE |
3076d3ceb1dSskrll 					    PCI_COMMAND_MEM_ENABLE |
3086d3ceb1dSskrll 					    PCI_COMMAND_MASTER_ENABLE | data);
3096d3ceb1dSskrll 				}
3106d3ceb1dSskrll 			}
3116d3ceb1dSskrll 			class = dino_conf_read(sc, tag, PCI_CLASS_REG);
3126d3ceb1dSskrll 			if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
3136d3ceb1dSskrll 			    PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)
3146d3ceb1dSskrll 				dino_enable_bus(sc, bus + 1);
3156d3ceb1dSskrll 		}
3166d3ceb1dSskrll 	}
3176d3ceb1dSskrll }
3186d3ceb1dSskrll 
3196d3ceb1dSskrll int
dino_maxdevs(void * v,int bus)3206d3ceb1dSskrll dino_maxdevs(void *v, int bus)
3216d3ceb1dSskrll {
3226d3ceb1dSskrll 	return 32;
3236d3ceb1dSskrll }
3246d3ceb1dSskrll 
3256d3ceb1dSskrll pcitag_t
dino_make_tag(void * v,int bus,int dev,int func)3266d3ceb1dSskrll dino_make_tag(void *v, int bus, int dev, int func)
3276d3ceb1dSskrll {
3286d3ceb1dSskrll 	if (bus > 255 || dev > 31 || func > 7)
3296d3ceb1dSskrll 		panic("dino_make_tag: bad request");
3306d3ceb1dSskrll 
3316d3ceb1dSskrll 	return (bus << 16) | (dev << 11) | (func << 8);
3326d3ceb1dSskrll }
3336d3ceb1dSskrll 
3346d3ceb1dSskrll void
dino_decompose_tag(void * v,pcitag_t tag,int * bus,int * dev,int * func)3356d3ceb1dSskrll dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func)
3366d3ceb1dSskrll {
3376d3ceb1dSskrll 	*bus = (tag >> 16) & 0xff;
3386d3ceb1dSskrll 	*dev = (tag >> 11) & 0x1f;
3396d3ceb1dSskrll 	*func= (tag >>  8) & 0x07;
3406d3ceb1dSskrll }
3416d3ceb1dSskrll 
3426d3ceb1dSskrll pcireg_t
dino_conf_read(void * v,pcitag_t tag,int reg)3436d3ceb1dSskrll dino_conf_read(void *v, pcitag_t tag, int reg)
3446d3ceb1dSskrll {
3456d3ceb1dSskrll 	struct dino_softc *sc = v;
3466d3ceb1dSskrll 	volatile struct dino_regs *r = sc->sc_regs;
3476d3ceb1dSskrll 	pcireg_t data;
3486d3ceb1dSskrll 	uint32_t pamr;
3496d3ceb1dSskrll 
350605f564fSmsaitoh 	if ((unsigned int)reg >= PCI_CONF_SIZE)
351605f564fSmsaitoh 		return (pcireg_t) -1;
352605f564fSmsaitoh 
353bb3c1460Smacallan 	/*
354bb3c1460Smacallan 	 * XXX
3550f66d627Smacallan 	 * thus sayeth the Dino manual:
3560f66d627Smacallan 	 * 7.7.1 Generating PCI Special Cycles thru PA I/O Space
3570f66d627Smacallan 	 * When the PCI_CONFIG_ADDR registers BUS_NUM is the equal to the
3580f66d627Smacallan 	 * DINO’s bus number, 8’h00, DEV_NUM and Function fields are all ones,
3590f66d627Smacallan 	 * and the REG_NUM field is all zeros the next write to PCI_CONFIG_DATA
3600f66d627Smacallan 	 * register will generate a special cycle on DINO’s PCI bus. If the
3610f66d627Smacallan 	 * BUS_NUM field does not equal DINO bus number then a type 1
3620f66d627Smacallan 	 * transaction will be forwarded to PCI as described above.
3630f66d627Smacallan 	 * Note: Dino is using a legal PCI configuration address to generate a
3640f66d627Smacallan 	 * PCI special cycle. System firmware and software should not attempt
3650f66d627Smacallan 	 * to read or write to this configuration address when walking the
3660f66d627Smacallan 	 * PCI bus through configuration address space.
367bb3c1460Smacallan 	 */
36852a4cb76Sskrll 	if ((tag & 0xff00) == 0xff00)
36952a4cb76Sskrll 		return -1;
370bb3c1460Smacallan 
3716d3ceb1dSskrll 	/* fix arbitration errata by disabling all pci devs on config read */
3726d3ceb1dSskrll 	pamr = r->pamr;
3736d3ceb1dSskrll 	r->pamr = 0;
3746d3ceb1dSskrll 
3756d3ceb1dSskrll 	r->pci_addr = tag | reg;
3766d3ceb1dSskrll 	data = r->pci_conf_data;
3776d3ceb1dSskrll 
3786d3ceb1dSskrll 	/* restore arbitration */
3796d3ceb1dSskrll 	r->pamr = pamr;
3806d3ceb1dSskrll 
3816d3ceb1dSskrll 	return le32toh(data);
3826d3ceb1dSskrll }
3836d3ceb1dSskrll 
3846d3ceb1dSskrll void
dino_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)3856d3ceb1dSskrll dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
3866d3ceb1dSskrll {
3876d3ceb1dSskrll 	struct dino_softc *sc = v;
3886d3ceb1dSskrll 	volatile struct dino_regs *r = sc->sc_regs;
3896d3ceb1dSskrll 	uint32_t pamr;
3906d3ceb1dSskrll 
391605f564fSmsaitoh 	if ((unsigned int)reg >= PCI_CONF_SIZE)
392605f564fSmsaitoh 		return;
393605f564fSmsaitoh 
394bb3c1460Smacallan 	/*
3950f66d627Smacallan 	 * don't try to access dev 1f / func 7, see comment in dino_conf_read()
396bb3c1460Smacallan 	 */
397bb3c1460Smacallan 	if ((tag & 0xff00) == 0xff00) return;
398bb3c1460Smacallan 
3996d3ceb1dSskrll 	/* fix arbitration errata by disabling all pci devs on config read */
4006d3ceb1dSskrll 	pamr = r->pamr;
4016d3ceb1dSskrll 	r->pamr = 0;
4026d3ceb1dSskrll 
4036d3ceb1dSskrll 	r->pci_addr = tag | reg;
4046d3ceb1dSskrll 	r->pci_conf_data = htole32(data);
4056d3ceb1dSskrll 
4066d3ceb1dSskrll 	/* fix coalescing config and io writes by interleaving w/ a read */
4076d3ceb1dSskrll 	r->pci_addr = tag | PCI_ID_REG;
4086d3ceb1dSskrll 	(void)r->pci_conf_data;
4096d3ceb1dSskrll 
4106d3ceb1dSskrll 	/* restore arbitration */
4116d3ceb1dSskrll 	r->pamr = pamr;
4126d3ceb1dSskrll }
4136d3ceb1dSskrll 
4146d3ceb1dSskrll int
dino_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)4156d3ceb1dSskrll dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
4166d3ceb1dSskrll {
4176d3ceb1dSskrll 	int line = pa->pa_intrline;
4186d3ceb1dSskrll 
4196d3ceb1dSskrll 	if (line == 0xff)
4206d3ceb1dSskrll 		return 1;
4216d3ceb1dSskrll 
4226d3ceb1dSskrll 	*ihp = line ;
4236d3ceb1dSskrll 
4246d3ceb1dSskrll 	return 0;
4256d3ceb1dSskrll }
4266d3ceb1dSskrll 
4276d3ceb1dSskrll const char *
dino_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)42826c6de43Schristos dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
4296d3ceb1dSskrll {
43026c6de43Schristos 	snprintf(buf, len, "irq %ld", ih);
4316d3ceb1dSskrll 	return buf;
4326d3ceb1dSskrll }
4336d3ceb1dSskrll 
4346d3ceb1dSskrll extern int cold;
4356d3ceb1dSskrll 
4366d3ceb1dSskrll 
4376d3ceb1dSskrll void *
dino_intr_establish(void * v,pci_intr_handle_t ih,int pri,int (* handler)(void *),void * arg)4386d3ceb1dSskrll dino_intr_establish(void *v, pci_intr_handle_t ih,
4396d3ceb1dSskrll     int pri, int (*handler)(void *), void *arg)
4406d3ceb1dSskrll {
4416d3ceb1dSskrll 	struct dino_softc *sc = v;
4426d3ceb1dSskrll 
4436d3ceb1dSskrll 	return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih);
4446d3ceb1dSskrll }
4456d3ceb1dSskrll 
4466d3ceb1dSskrll void
dino_intr_disestablish(void * v,void * cookie)4476d3ceb1dSskrll dino_intr_disestablish(void *v, void *cookie)
4486d3ceb1dSskrll {
4496d3ceb1dSskrll 	/* XXX Implement me */
4506d3ceb1dSskrll }
4516d3ceb1dSskrll 
4526d3ceb1dSskrll 
4536d3ceb1dSskrll #if NCARDBUS > 0
4546d3ceb1dSskrll void *
dino_alloc_parent(device_t self,struct pci_attach_args * pa,int io)4556d3ceb1dSskrll dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io)
4566d3ceb1dSskrll {
4576d3ceb1dSskrll 	struct dino_softc *sc = pa->pa_pc->_cookie;
4586d3ceb1dSskrll 	struct extent *ex;
4596d3ceb1dSskrll 	bus_space_tag_t tag;
4606d3ceb1dSskrll 	bus_addr_t start;
4616d3ceb1dSskrll 	bus_size_t size;
4626d3ceb1dSskrll 
4636d3ceb1dSskrll 	if (io) {
4646d3ceb1dSskrll 		ex = sc->sc_ioex;
4656d3ceb1dSskrll 		tag = pa->pa_iot;
4666d3ceb1dSskrll 		start = 0xa000;
4676d3ceb1dSskrll 		size = 0x1000;
4686d3ceb1dSskrll 	} else {
4696d3ceb1dSskrll 		ex = hppa_io_extent;
4706d3ceb1dSskrll 		tag = pa->pa_memt;
4716d3ceb1dSskrll 		start = ex->ex_start; /* XXX or 0xf0800000? */
4726d3ceb1dSskrll 		size = DINO_MEM_CHUNK;
4736d3ceb1dSskrll 	}
4746d3ceb1dSskrll 
4756d3ceb1dSskrll 	if (extent_alloc_subregion(ex, start, ex->ex_end, size, size,
4766d3ceb1dSskrll 	    EX_NOBOUNDARY, EX_NOWAIT, &start))
4776d3ceb1dSskrll 		return NULL;
4786d3ceb1dSskrll 	extent_free(ex, start, size, EX_NOWAIT);
4796d3ceb1dSskrll 	return rbus_new_root_share(tag, ex, start, size, start);
4806d3ceb1dSskrll }
4816d3ceb1dSskrll #endif
4826d3ceb1dSskrll 
4836d3ceb1dSskrll int
dino_iomap(void * v,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)4846d3ceb1dSskrll dino_iomap(void *v, bus_addr_t bpa, bus_size_t size,
4856d3ceb1dSskrll     int flags, bus_space_handle_t *bshp)
4866d3ceb1dSskrll {
4876d3ceb1dSskrll 	struct dino_softc *sc = v;
4886d3ceb1dSskrll 	int error;
4896d3ceb1dSskrll 
4906d3ceb1dSskrll 	if (!(flags & BUS_SPACE_MAP_NOEXTENT) &&
4916d3ceb1dSskrll 	    (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT)))
4926d3ceb1dSskrll 		return error;
4936d3ceb1dSskrll 
4946d3ceb1dSskrll 	if (bshp)
4956d3ceb1dSskrll 		*bshp = bpa;
4966d3ceb1dSskrll 
4976d3ceb1dSskrll 	return 0;
4986d3ceb1dSskrll }
4996d3ceb1dSskrll 
5006d3ceb1dSskrll int
dino_memmap(void * v,bus_addr_t bpa,bus_size_t size,int flags,bus_space_handle_t * bshp)5016d3ceb1dSskrll dino_memmap(void *v, bus_addr_t bpa, bus_size_t size,
5026d3ceb1dSskrll     int flags, bus_space_handle_t *bshp)
5036d3ceb1dSskrll {
5046d3ceb1dSskrll 	struct dino_softc *sc = v;
5056d3ceb1dSskrll 	volatile struct dino_regs *r = sc->sc_regs;
5066d3ceb1dSskrll 	uint32_t reg;
5076d3ceb1dSskrll 	int error;
5086d3ceb1dSskrll 
5096d3ceb1dSskrll 	reg = r->io_addr_en;
5106d3ceb1dSskrll 	reg |= 1 << ((bpa >> 23) & 0x1f);
5116d3ceb1dSskrll #ifdef DEBUG
5126d3ceb1dSskrll 	if (reg & 0x80000001)
5136d3ceb1dSskrll 		panic("mapping outside the mem extent range");
5146d3ceb1dSskrll #endif
5156d3ceb1dSskrll 	if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp)))
5166d3ceb1dSskrll 		return error;
5176d3ceb1dSskrll 	++sc->sc_memrefcount[((bpa >> 23) & 0x1f)];
5186d3ceb1dSskrll 	/* map into the upper bus space, if not yet mapped this 8M */
5196d3ceb1dSskrll 	if (reg != r->io_addr_en)
5206d3ceb1dSskrll 		r->io_addr_en = reg;
5216d3ceb1dSskrll 	return 0;
5226d3ceb1dSskrll }
5236d3ceb1dSskrll 
5246d3ceb1dSskrll int
dino_subregion(void * v,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)5256d3ceb1dSskrll dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
5266d3ceb1dSskrll     bus_size_t size, bus_space_handle_t *nbshp)
5276d3ceb1dSskrll {
5286d3ceb1dSskrll 	*nbshp = bsh + offset;
5296d3ceb1dSskrll 	return 0;
5306d3ceb1dSskrll }
5316d3ceb1dSskrll 
5326d3ceb1dSskrll int
dino_ioalloc(void * v,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t align,bus_size_t boundary,int flags,bus_addr_t * addrp,bus_space_handle_t * bshp)5336d3ceb1dSskrll dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
5346d3ceb1dSskrll     bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
5356d3ceb1dSskrll     bus_space_handle_t *bshp)
5366d3ceb1dSskrll {
5376d3ceb1dSskrll 	struct dino_softc *sc = v;
5386d3ceb1dSskrll 	struct extent *ex = sc->sc_ioex;
5396d3ceb1dSskrll 	bus_addr_t bpa;
5406d3ceb1dSskrll 	int error;
5416d3ceb1dSskrll 
5426d3ceb1dSskrll 	if (rstart < ex->ex_start || rend > ex->ex_end)
5436d3ceb1dSskrll 		panic("dino_ioalloc: bad region start/end");
5446d3ceb1dSskrll 
5456d3ceb1dSskrll 	if ((error = extent_alloc_subregion(ex, rstart, rend, size,
5466d3ceb1dSskrll 	    align, boundary, EX_NOWAIT, &bpa)))
5476d3ceb1dSskrll 		return error;
5486d3ceb1dSskrll 
5496d3ceb1dSskrll 	if (addrp)
5506d3ceb1dSskrll 		*addrp = bpa;
5516d3ceb1dSskrll 	if (bshp)
5526d3ceb1dSskrll 		*bshp = bpa;
5536d3ceb1dSskrll 
5546d3ceb1dSskrll 	return 0;
5556d3ceb1dSskrll }
5566d3ceb1dSskrll 
5576d3ceb1dSskrll int
dino_memalloc(void * v,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t align,bus_size_t boundary,int flags,bus_addr_t * addrp,bus_space_handle_t * bshp)5586d3ceb1dSskrll dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
5596d3ceb1dSskrll     bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp,
5606d3ceb1dSskrll     bus_space_handle_t *bshp)
5616d3ceb1dSskrll {
5626d3ceb1dSskrll 	struct dino_softc *sc = v;
5636d3ceb1dSskrll 	volatile struct dino_regs *r = sc->sc_regs;
5646d3ceb1dSskrll 	uint32_t reg;
5656d3ceb1dSskrll 	int i, error;
5666d3ceb1dSskrll 
5676d3ceb1dSskrll 	/*
5686d3ceb1dSskrll 	 * Allow allocation only when PCI MEM is already mapped.
5696d3ceb1dSskrll 	 * Needed to avoid allocation of I/O space used by devices that
5706d3ceb1dSskrll 	 * have no driver in the current kernel.
5716d3ceb1dSskrll 	 * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only.
5726d3ceb1dSskrll 	 */
5736d3ceb1dSskrll 	reg = r->io_addr_en;
5746d3ceb1dSskrll 	if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0)
5756d3ceb1dSskrll 		return -1;
5766d3ceb1dSskrll 	/* Find used PCI MEM and narrow allocateble region down to it. */
5776d3ceb1dSskrll 	for (i = 1; i < 31; i++)
5786d3ceb1dSskrll 		if ((reg & 1 << i) != 0) {
5796d3ceb1dSskrll 			rstart = HPPA_IOSPACE | i << 23;
5806d3ceb1dSskrll 			rend = (HPPA_IOSPACE | (i + 1) << 23) - 1;
5816d3ceb1dSskrll 			break;
5826d3ceb1dSskrll 		}
5836d3ceb1dSskrll 	if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align,
5846d3ceb1dSskrll 	    boundary, flags, addrp, bshp)))
5856d3ceb1dSskrll 		return error;
5866d3ceb1dSskrll 	++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)];
5876d3ceb1dSskrll 	return 0;
5886d3ceb1dSskrll }
5896d3ceb1dSskrll 
5906d3ceb1dSskrll void
dino_unmap(void * v,bus_space_handle_t bsh,bus_size_t size)5916d3ceb1dSskrll dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
5926d3ceb1dSskrll {
5936d3ceb1dSskrll 	struct dino_softc *sc = v;
5946d3ceb1dSskrll 	volatile struct dino_regs *r = sc->sc_regs;
5956d3ceb1dSskrll 
5966d3ceb1dSskrll 	if (bsh & HPPA_IOSPACE) {
5976d3ceb1dSskrll 		bus_space_unmap(sc->sc_bt, bsh, size);
5986d3ceb1dSskrll 		if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0)
5996d3ceb1dSskrll 			/* Unmap the upper PCI MEM space. */
6006d3ceb1dSskrll 			r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f));
6016d3ceb1dSskrll 	} else {
6026d3ceb1dSskrll 		/* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */
6036d3ceb1dSskrll 		if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT))
6046d3ceb1dSskrll 			printf("dino_unmap: ps 0x%lx, size 0x%lx\n"
6056d3ceb1dSskrll 			    "dino_unmap: can't free region\n", bsh, size);
6066d3ceb1dSskrll 	}
6076d3ceb1dSskrll }
6086d3ceb1dSskrll 
6096d3ceb1dSskrll void
dino_free(void * v,bus_space_handle_t bh,bus_size_t size)6106d3ceb1dSskrll dino_free(void *v, bus_space_handle_t bh, bus_size_t size)
6116d3ceb1dSskrll {
6126d3ceb1dSskrll 	/* should be enough */
6136d3ceb1dSskrll 	dino_unmap(v, bh, size);
6146d3ceb1dSskrll }
6156d3ceb1dSskrll 
6166d3ceb1dSskrll void
dino_barrier(void * v,bus_space_handle_t h,bus_size_t o,bus_size_t l,int op)6176d3ceb1dSskrll dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op)
6186d3ceb1dSskrll {
6196d3ceb1dSskrll 	sync_caches();
6206d3ceb1dSskrll }
6216d3ceb1dSskrll 
6226d3ceb1dSskrll void*
dino_vaddr(void * v,bus_space_handle_t h)6236d3ceb1dSskrll dino_vaddr(void *v, bus_space_handle_t h)
6246d3ceb1dSskrll {
6256d3ceb1dSskrll 	struct dino_softc *sc = v;
6266d3ceb1dSskrll 
6276d3ceb1dSskrll 	return bus_space_vaddr(sc->sc_bt, h);
6286d3ceb1dSskrll }
6296d3ceb1dSskrll 
6306d3ceb1dSskrll paddr_t
dino_mmap(void * v,bus_addr_t addr,off_t off,int prot,int flags)6316d3ceb1dSskrll dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags)
6326d3ceb1dSskrll {
633f64266f9Smacallan 	return btop(addr + off);
6346d3ceb1dSskrll }
6356d3ceb1dSskrll 
6366d3ceb1dSskrll uint8_t
dino_r1(void * v,bus_space_handle_t h,bus_size_t o)6376d3ceb1dSskrll dino_r1(void *v, bus_space_handle_t h, bus_size_t o)
6386d3ceb1dSskrll {
6396d3ceb1dSskrll 	h += o;
6406d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
6416d3ceb1dSskrll 		return *(volatile uint8_t *)h;
6426d3ceb1dSskrll 	else {
6436d3ceb1dSskrll 		struct dino_softc *sc = v;
6446d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
6456d3ceb1dSskrll 
6466d3ceb1dSskrll 		r->pci_addr = h;
6476d3ceb1dSskrll 		return *((volatile uint8_t *)&r->pci_io_data + (h & 3));
6486d3ceb1dSskrll 	}
6496d3ceb1dSskrll }
6506d3ceb1dSskrll 
6516d3ceb1dSskrll uint16_t
dino_r2(void * v,bus_space_handle_t h,bus_size_t o)6526d3ceb1dSskrll dino_r2(void *v, bus_space_handle_t h, bus_size_t o)
6536d3ceb1dSskrll {
6546d3ceb1dSskrll 	volatile uint16_t *p;
6556d3ceb1dSskrll 
6566d3ceb1dSskrll 	h += o;
6576d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
6586d3ceb1dSskrll 		p = (volatile uint16_t *)h;
6596d3ceb1dSskrll 	else {
6606d3ceb1dSskrll 		struct dino_softc *sc = v;
6616d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
6626d3ceb1dSskrll 
6636d3ceb1dSskrll 		r->pci_addr = h;
6646d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
6656d3ceb1dSskrll 		if (h & 2)
6666d3ceb1dSskrll 			p++;
6676d3ceb1dSskrll 	}
6686d3ceb1dSskrll 	return le16toh(*p);
6696d3ceb1dSskrll }
6706d3ceb1dSskrll 
6716d3ceb1dSskrll uint32_t
dino_r4(void * v,bus_space_handle_t h,bus_size_t o)6726d3ceb1dSskrll dino_r4(void *v, bus_space_handle_t h, bus_size_t o)
6736d3ceb1dSskrll {
6746d3ceb1dSskrll 	uint32_t data;
6756d3ceb1dSskrll 
6766d3ceb1dSskrll 	h += o;
6776d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
6786d3ceb1dSskrll 		data = *(volatile uint32_t *)h;
6796d3ceb1dSskrll 	else {
6806d3ceb1dSskrll 		struct dino_softc *sc = v;
6816d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
6826d3ceb1dSskrll 
6836d3ceb1dSskrll 		r->pci_addr = h;
6846d3ceb1dSskrll 		data = r->pci_io_data;
6856d3ceb1dSskrll 	}
6866d3ceb1dSskrll 
6876d3ceb1dSskrll 	return le32toh(data);
6886d3ceb1dSskrll }
6896d3ceb1dSskrll 
6906d3ceb1dSskrll uint64_t
dino_r8(void * v,bus_space_handle_t h,bus_size_t o)6916d3ceb1dSskrll dino_r8(void *v, bus_space_handle_t h, bus_size_t o)
6926d3ceb1dSskrll {
6936d3ceb1dSskrll 	uint64_t data;
6946d3ceb1dSskrll 
6956d3ceb1dSskrll 	h += o;
6966d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
6976d3ceb1dSskrll 		data = *(volatile uint64_t *)h;
6986d3ceb1dSskrll 	else
6996d3ceb1dSskrll 		panic("dino_r8: not implemented");
7006d3ceb1dSskrll 
7016d3ceb1dSskrll 	return le64toh(data);
7026d3ceb1dSskrll }
7036d3ceb1dSskrll 
704*dbeed521Smacallan uint16_t
dino_rs2(void * v,bus_space_handle_t h,bus_size_t o)705*dbeed521Smacallan dino_rs2(void *v, bus_space_handle_t h, bus_size_t o)
706*dbeed521Smacallan {
707*dbeed521Smacallan 	volatile uint16_t *p;
708*dbeed521Smacallan 
709*dbeed521Smacallan 	h += o;
710*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
711*dbeed521Smacallan 		p = (volatile uint16_t *)h;
712*dbeed521Smacallan 	else {
713*dbeed521Smacallan 		struct dino_softc *sc = v;
714*dbeed521Smacallan 		volatile struct dino_regs *r = sc->sc_regs;
715*dbeed521Smacallan 
716*dbeed521Smacallan 		r->pci_addr = h;
717*dbeed521Smacallan 		p = (volatile uint16_t *)&r->pci_io_data;
718*dbeed521Smacallan 		if (h & 2)
719*dbeed521Smacallan 			p++;
720*dbeed521Smacallan 	}
721*dbeed521Smacallan 	return *p;
722*dbeed521Smacallan }
723*dbeed521Smacallan 
724*dbeed521Smacallan uint32_t
dino_rs4(void * v,bus_space_handle_t h,bus_size_t o)725*dbeed521Smacallan dino_rs4(void *v, bus_space_handle_t h, bus_size_t o)
726*dbeed521Smacallan {
727*dbeed521Smacallan 	uint32_t data;
728*dbeed521Smacallan 
729*dbeed521Smacallan 	h += o;
730*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
731*dbeed521Smacallan 		data = *(volatile uint32_t *)h;
732*dbeed521Smacallan 	else {
733*dbeed521Smacallan 		struct dino_softc *sc = v;
734*dbeed521Smacallan 		volatile struct dino_regs *r = sc->sc_regs;
735*dbeed521Smacallan 
736*dbeed521Smacallan 		r->pci_addr = h;
737*dbeed521Smacallan 		data = r->pci_io_data;
738*dbeed521Smacallan 	}
739*dbeed521Smacallan 
740*dbeed521Smacallan 	return data;
741*dbeed521Smacallan }
742*dbeed521Smacallan 
743*dbeed521Smacallan uint64_t
dino_rs8(void * v,bus_space_handle_t h,bus_size_t o)744*dbeed521Smacallan dino_rs8(void *v, bus_space_handle_t h, bus_size_t o)
745*dbeed521Smacallan {
746*dbeed521Smacallan 	uint64_t data;
747*dbeed521Smacallan 
748*dbeed521Smacallan 	h += o;
749*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
750*dbeed521Smacallan 		data = *(volatile uint64_t *)h;
751*dbeed521Smacallan 	else
752*dbeed521Smacallan 		panic("dino_r8: not implemented");
753*dbeed521Smacallan 
754*dbeed521Smacallan 	return data;
755*dbeed521Smacallan }
756*dbeed521Smacallan 
7576d3ceb1dSskrll void
dino_w1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv)7586d3ceb1dSskrll dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv)
7596d3ceb1dSskrll {
7606d3ceb1dSskrll 	h += o;
7616d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
7626d3ceb1dSskrll 		*(volatile uint8_t *)h = vv;
7636d3ceb1dSskrll 	else {
7646d3ceb1dSskrll 		struct dino_softc *sc = v;
7656d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
7666d3ceb1dSskrll 
7676d3ceb1dSskrll 		r->pci_addr = h;
7686d3ceb1dSskrll 		*((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv;
7696d3ceb1dSskrll 	}
7706d3ceb1dSskrll }
7716d3ceb1dSskrll 
7726d3ceb1dSskrll void
dino_w2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv)7736d3ceb1dSskrll dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv)
7746d3ceb1dSskrll {
7756d3ceb1dSskrll 	volatile uint16_t *p;
7766d3ceb1dSskrll 
7776d3ceb1dSskrll 	h += o;
7786d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
7796d3ceb1dSskrll 		p = (volatile uint16_t *)h;
7806d3ceb1dSskrll 	else {
7816d3ceb1dSskrll 		struct dino_softc *sc = v;
7826d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
7836d3ceb1dSskrll 
7846d3ceb1dSskrll 		r->pci_addr = h;
7856d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
7866d3ceb1dSskrll 		if (h & 2)
7876d3ceb1dSskrll 			p++;
7886d3ceb1dSskrll 	}
7896d3ceb1dSskrll 
7906d3ceb1dSskrll 	*p = htole16(vv);
7916d3ceb1dSskrll }
7926d3ceb1dSskrll 
7936d3ceb1dSskrll void
dino_w4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv)7946d3ceb1dSskrll dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv)
7956d3ceb1dSskrll {
7966d3ceb1dSskrll 	h += o;
7976d3ceb1dSskrll 	vv = htole32(vv);
7986d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
7996d3ceb1dSskrll 		*(volatile uint32_t *)h = vv;
8006d3ceb1dSskrll 	else {
8016d3ceb1dSskrll 		struct dino_softc *sc = v;
8026d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
8036d3ceb1dSskrll 
8046d3ceb1dSskrll 		r->pci_addr = h;
8056d3ceb1dSskrll 		r->pci_io_data = vv;
8066d3ceb1dSskrll 	}
8076d3ceb1dSskrll }
8086d3ceb1dSskrll 
8096d3ceb1dSskrll void
dino_w8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv)8106d3ceb1dSskrll dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv)
8116d3ceb1dSskrll {
8126d3ceb1dSskrll 	h += o;
8136d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
8146d3ceb1dSskrll 		*(volatile uint64_t *)h = htole64(vv);
8156d3ceb1dSskrll 	else
8166d3ceb1dSskrll 		panic("dino_w8: not implemented");
8176d3ceb1dSskrll }
8186d3ceb1dSskrll 
819*dbeed521Smacallan void
dino_ws2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv)820*dbeed521Smacallan dino_ws2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv)
821*dbeed521Smacallan {
822*dbeed521Smacallan 	volatile uint16_t *p;
823*dbeed521Smacallan 
824*dbeed521Smacallan 	h += o;
825*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
826*dbeed521Smacallan 		p = (volatile uint16_t *)h;
827*dbeed521Smacallan 	else {
828*dbeed521Smacallan 		struct dino_softc *sc = v;
829*dbeed521Smacallan 		volatile struct dino_regs *r = sc->sc_regs;
830*dbeed521Smacallan 
831*dbeed521Smacallan 		r->pci_addr = h;
832*dbeed521Smacallan 		p = (volatile uint16_t *)&r->pci_io_data;
833*dbeed521Smacallan 		if (h & 2)
834*dbeed521Smacallan 			p++;
835*dbeed521Smacallan 	}
836*dbeed521Smacallan 
837*dbeed521Smacallan 	*p = vv;
838*dbeed521Smacallan }
839*dbeed521Smacallan 
840*dbeed521Smacallan void
dino_ws4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv)841*dbeed521Smacallan dino_ws4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv)
842*dbeed521Smacallan {
843*dbeed521Smacallan 	h += o;
844*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
845*dbeed521Smacallan 		*(volatile uint32_t *)h = vv;
846*dbeed521Smacallan 	else {
847*dbeed521Smacallan 		struct dino_softc *sc = v;
848*dbeed521Smacallan 		volatile struct dino_regs *r = sc->sc_regs;
849*dbeed521Smacallan 
850*dbeed521Smacallan 		r->pci_addr = h;
851*dbeed521Smacallan 		r->pci_io_data = vv;
852*dbeed521Smacallan 	}
853*dbeed521Smacallan }
854*dbeed521Smacallan 
855*dbeed521Smacallan void
dino_ws8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv)856*dbeed521Smacallan dino_ws8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv)
857*dbeed521Smacallan {
858*dbeed521Smacallan 	h += o;
859*dbeed521Smacallan 	if (h & HPPA_IOSPACE)
860*dbeed521Smacallan 		*(volatile uint64_t *)h = vv;
861*dbeed521Smacallan 	else
862*dbeed521Smacallan 		panic("dino_w8: not implemented");
863*dbeed521Smacallan }
8646d3ceb1dSskrll 
8656d3ceb1dSskrll void
dino_rm_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t * a,bus_size_t c)8666d3ceb1dSskrll dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
8676d3ceb1dSskrll {
8686d3ceb1dSskrll 	volatile uint8_t *p;
8696d3ceb1dSskrll 
8706d3ceb1dSskrll 	h += o;
8716d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
8726d3ceb1dSskrll 		p = (volatile uint8_t *)h;
8736d3ceb1dSskrll 	else {
8746d3ceb1dSskrll 		struct dino_softc *sc = v;
8756d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
8766d3ceb1dSskrll 
8776d3ceb1dSskrll 		r->pci_addr = h;
8786d3ceb1dSskrll 		p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
8796d3ceb1dSskrll 	}
8806d3ceb1dSskrll 
8816d3ceb1dSskrll 	while (c--)
8826d3ceb1dSskrll 		*a++ = *p;
8836d3ceb1dSskrll }
8846d3ceb1dSskrll 
8856d3ceb1dSskrll void
dino_rm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)8866d3ceb1dSskrll dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
8876d3ceb1dSskrll {
8886d3ceb1dSskrll 	volatile uint16_t *p;
8896d3ceb1dSskrll 
8906d3ceb1dSskrll 	h += o;
8916d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
8926d3ceb1dSskrll 		p = (volatile uint16_t *)h;
8936d3ceb1dSskrll 	else {
8946d3ceb1dSskrll 		struct dino_softc *sc = v;
8956d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
8966d3ceb1dSskrll 
8976d3ceb1dSskrll 		r->pci_addr = h;
8986d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
8996d3ceb1dSskrll 		if (h & 2)
9006d3ceb1dSskrll 			p++;
9016d3ceb1dSskrll 	}
9026d3ceb1dSskrll 
9036d3ceb1dSskrll 	while (c--)
9046d3ceb1dSskrll 		*a++ = le16toh(*p);
9056d3ceb1dSskrll }
9066d3ceb1dSskrll 
9076d3ceb1dSskrll void
dino_rm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)9086d3ceb1dSskrll dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
9096d3ceb1dSskrll {
9106d3ceb1dSskrll 	volatile uint32_t *p;
9116d3ceb1dSskrll 
9126d3ceb1dSskrll 	h += o;
9136d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
9146d3ceb1dSskrll 		p = (volatile uint32_t *)h;
9156d3ceb1dSskrll 	else {
9166d3ceb1dSskrll 		struct dino_softc *sc = v;
9176d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
9186d3ceb1dSskrll 
9196d3ceb1dSskrll 		r->pci_addr = h;
9206d3ceb1dSskrll 		p = (volatile uint32_t *)&r->pci_io_data;
9216d3ceb1dSskrll 	}
9226d3ceb1dSskrll 
9236d3ceb1dSskrll 	while (c--)
9246d3ceb1dSskrll 		*a++ = le32toh(*p);
9256d3ceb1dSskrll }
9266d3ceb1dSskrll 
9276d3ceb1dSskrll void
dino_rm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)9286d3ceb1dSskrll dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
9296d3ceb1dSskrll {
9306d3ceb1dSskrll 	panic("dino_rm_8: not implemented");
9316d3ceb1dSskrll }
9326d3ceb1dSskrll 
9336d3ceb1dSskrll void
dino_wm_1(void * v,bus_space_handle_t h,bus_size_t o,const uint8_t * a,bus_size_t c)9346d3ceb1dSskrll dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
9356d3ceb1dSskrll {
9366d3ceb1dSskrll 	volatile uint8_t *p;
9376d3ceb1dSskrll 
9386d3ceb1dSskrll 	h += o;
9396d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
9406d3ceb1dSskrll 		p = (volatile uint8_t *)h;
9416d3ceb1dSskrll 	else {
9426d3ceb1dSskrll 		struct dino_softc *sc = v;
9436d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
9446d3ceb1dSskrll 
9456d3ceb1dSskrll 		r->pci_addr = h;
9466d3ceb1dSskrll 		p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
9476d3ceb1dSskrll 	}
9486d3ceb1dSskrll 
9496d3ceb1dSskrll 	while (c--)
9506d3ceb1dSskrll 		*p = *a++;
9516d3ceb1dSskrll }
9526d3ceb1dSskrll 
9536d3ceb1dSskrll void
dino_wm_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)9546d3ceb1dSskrll dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
9556d3ceb1dSskrll {
9566d3ceb1dSskrll 	volatile uint16_t *p;
9576d3ceb1dSskrll 
9586d3ceb1dSskrll 	h += o;
9596d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
9606d3ceb1dSskrll 		p = (volatile uint16_t *)h;
9616d3ceb1dSskrll 	else {
9626d3ceb1dSskrll 		struct dino_softc *sc = v;
9636d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
9646d3ceb1dSskrll 
9656d3ceb1dSskrll 		r->pci_addr = h;
9666d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
9676d3ceb1dSskrll 		if (h & 2)
9686d3ceb1dSskrll 			p++;
9696d3ceb1dSskrll 	}
9706d3ceb1dSskrll 
9716d3ceb1dSskrll 	while (c--)
9726d3ceb1dSskrll 		*p = htole16(*a++);
9736d3ceb1dSskrll }
9746d3ceb1dSskrll 
9756d3ceb1dSskrll void
dino_wm_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)9766d3ceb1dSskrll dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
9776d3ceb1dSskrll {
9786d3ceb1dSskrll 	volatile uint32_t *p;
9796d3ceb1dSskrll 
9806d3ceb1dSskrll 	h += o;
9816d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
9826d3ceb1dSskrll 		p = (volatile uint32_t *)h;
9836d3ceb1dSskrll 	else {
9846d3ceb1dSskrll 		struct dino_softc *sc = v;
9856d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
9866d3ceb1dSskrll 
9876d3ceb1dSskrll 		r->pci_addr = h;
9886d3ceb1dSskrll 		p = (volatile uint32_t *)&r->pci_io_data;
9896d3ceb1dSskrll 	}
9906d3ceb1dSskrll 
9916d3ceb1dSskrll 	while (c--)
9926d3ceb1dSskrll 		*p = htole32(*a++);
9936d3ceb1dSskrll }
9946d3ceb1dSskrll 
9956d3ceb1dSskrll void
dino_wm_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)9966d3ceb1dSskrll dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
9976d3ceb1dSskrll {
9986d3ceb1dSskrll 	panic("dino_wm_8: not implemented");
9996d3ceb1dSskrll }
10006d3ceb1dSskrll 
10016d3ceb1dSskrll void
dino_sm_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv,bus_size_t c)10026d3ceb1dSskrll dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
10036d3ceb1dSskrll {
10046d3ceb1dSskrll 	volatile uint8_t *p;
10056d3ceb1dSskrll 
10066d3ceb1dSskrll 	h += o;
10076d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
10086d3ceb1dSskrll 		p = (volatile uint8_t *)h;
10096d3ceb1dSskrll 	else {
10106d3ceb1dSskrll 		struct dino_softc *sc = v;
10116d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
10126d3ceb1dSskrll 
10136d3ceb1dSskrll 		r->pci_addr = h;
10146d3ceb1dSskrll 		p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
10156d3ceb1dSskrll 	}
10166d3ceb1dSskrll 
10176d3ceb1dSskrll 	while (c--)
10186d3ceb1dSskrll 		*p = vv;
10196d3ceb1dSskrll }
10206d3ceb1dSskrll 
10216d3ceb1dSskrll void
dino_sm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv,bus_size_t c)10226d3ceb1dSskrll dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
10236d3ceb1dSskrll {
10246d3ceb1dSskrll 	volatile uint16_t *p;
10256d3ceb1dSskrll 
10266d3ceb1dSskrll 	h += o;
10276d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
10286d3ceb1dSskrll 		p = (volatile uint16_t *)h;
10296d3ceb1dSskrll 	else {
10306d3ceb1dSskrll 		struct dino_softc *sc = v;
10316d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
10326d3ceb1dSskrll 
10336d3ceb1dSskrll 		r->pci_addr = h;
10346d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
10356d3ceb1dSskrll 		if (h & 2)
10366d3ceb1dSskrll 			p++;
10376d3ceb1dSskrll 	}
10386d3ceb1dSskrll 
10396d3ceb1dSskrll 	while (c--)
10406d3ceb1dSskrll 		*p = htole16(vv);
10416d3ceb1dSskrll }
10426d3ceb1dSskrll 
10436d3ceb1dSskrll void
dino_sm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv,bus_size_t c)10446d3ceb1dSskrll dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
10456d3ceb1dSskrll {
10466d3ceb1dSskrll 	volatile uint32_t *p;
10476d3ceb1dSskrll 
10486d3ceb1dSskrll 	h += o;
10496d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
10506d3ceb1dSskrll 		p = (volatile uint32_t *)h;
10516d3ceb1dSskrll 	else {
10526d3ceb1dSskrll 		struct dino_softc *sc = v;
10536d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
10546d3ceb1dSskrll 
10556d3ceb1dSskrll 		r->pci_addr = h;
10566d3ceb1dSskrll 		p = (volatile uint32_t *)&r->pci_io_data;
10576d3ceb1dSskrll 	}
10586d3ceb1dSskrll 
10596d3ceb1dSskrll 	while (c--)
10606d3ceb1dSskrll 		*p = htole32(vv);
10616d3ceb1dSskrll }
10626d3ceb1dSskrll 
10636d3ceb1dSskrll void
dino_sm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv,bus_size_t c)10646d3ceb1dSskrll dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
10656d3ceb1dSskrll {
10666d3ceb1dSskrll 	panic("dino_sm_8: not implemented");
10676d3ceb1dSskrll }
10686d3ceb1dSskrll 
10696d3ceb1dSskrll void
dino_rrm_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)10706d3ceb1dSskrll dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o,
10716d3ceb1dSskrll     uint16_t *a, bus_size_t c)
10726d3ceb1dSskrll {
10736d3ceb1dSskrll 	volatile uint16_t *p;
10746d3ceb1dSskrll 
10756d3ceb1dSskrll 	h += o;
10766d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
10776d3ceb1dSskrll 		p = (volatile uint16_t *)h;
10786d3ceb1dSskrll 	else {
10796d3ceb1dSskrll 		struct dino_softc *sc = v;
10806d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
10816d3ceb1dSskrll 
10826d3ceb1dSskrll 		r->pci_addr = h;
10836d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
10846d3ceb1dSskrll 		if (h & 2)
10856d3ceb1dSskrll 			p++;
10866d3ceb1dSskrll 	}
10876d3ceb1dSskrll 
10886d3ceb1dSskrll 	while (c--)
10896d3ceb1dSskrll 		*a++ = *p;
10906d3ceb1dSskrll }
10916d3ceb1dSskrll 
10926d3ceb1dSskrll void
dino_rrm_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)10936d3ceb1dSskrll dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o,
10946d3ceb1dSskrll     uint32_t *a, bus_size_t c)
10956d3ceb1dSskrll {
10966d3ceb1dSskrll 	volatile uint32_t *p;
10976d3ceb1dSskrll 
10986d3ceb1dSskrll 	h += o;
10996d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
11006d3ceb1dSskrll 		p = (volatile uint32_t *)h;
11016d3ceb1dSskrll 	else {
11026d3ceb1dSskrll 		struct dino_softc *sc = v;
11036d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
11046d3ceb1dSskrll 
11056d3ceb1dSskrll 		r->pci_addr = h;
11066d3ceb1dSskrll 		p = (volatile uint32_t *)&r->pci_io_data;
11076d3ceb1dSskrll 	}
11086d3ceb1dSskrll 
11096d3ceb1dSskrll 	while (c--)
11106d3ceb1dSskrll 		*a++ = *p;
11116d3ceb1dSskrll }
11126d3ceb1dSskrll 
11136d3ceb1dSskrll void
dino_rrm_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)11146d3ceb1dSskrll dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o,
11156d3ceb1dSskrll     uint64_t *a, bus_size_t c)
11166d3ceb1dSskrll {
11176d3ceb1dSskrll 	panic("dino_rrm_8: not implemented");
11186d3ceb1dSskrll }
11196d3ceb1dSskrll 
11206d3ceb1dSskrll void
dino_wrm_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)11216d3ceb1dSskrll dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o,
11226d3ceb1dSskrll     const uint16_t *a, bus_size_t c)
11236d3ceb1dSskrll {
11246d3ceb1dSskrll 	volatile uint16_t *p;
11256d3ceb1dSskrll 
11266d3ceb1dSskrll 	h += o;
11276d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
11286d3ceb1dSskrll 		p = (volatile uint16_t *)h;
11296d3ceb1dSskrll 	else {
11306d3ceb1dSskrll 		struct dino_softc *sc = v;
11316d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
11326d3ceb1dSskrll 
11336d3ceb1dSskrll 		r->pci_addr = h;
11346d3ceb1dSskrll 		p = (volatile uint16_t *)&r->pci_io_data;
11356d3ceb1dSskrll 		if (h & 2)
11366d3ceb1dSskrll 			p++;
11376d3ceb1dSskrll 	}
11386d3ceb1dSskrll 
11396d3ceb1dSskrll 	while (c--)
11406d3ceb1dSskrll 		*p = *a++;
11416d3ceb1dSskrll }
11426d3ceb1dSskrll 
11436d3ceb1dSskrll void
dino_wrm_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)11446d3ceb1dSskrll dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o,
11456d3ceb1dSskrll     const uint32_t *a, bus_size_t c)
11466d3ceb1dSskrll {
11476d3ceb1dSskrll 	volatile uint32_t *p;
11486d3ceb1dSskrll 
11496d3ceb1dSskrll 	h += o;
11506d3ceb1dSskrll 	if (h & HPPA_IOSPACE)
11516d3ceb1dSskrll 		p = (volatile uint32_t *)h;
11526d3ceb1dSskrll 	else {
11536d3ceb1dSskrll 		struct dino_softc *sc = v;
11546d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
11556d3ceb1dSskrll 
11566d3ceb1dSskrll 		r->pci_addr = h;
11576d3ceb1dSskrll 		p = (volatile uint32_t *)&r->pci_io_data;
11586d3ceb1dSskrll 	}
11596d3ceb1dSskrll 
11606d3ceb1dSskrll 	while (c--)
11616d3ceb1dSskrll 		*p = *a++;
11626d3ceb1dSskrll }
11636d3ceb1dSskrll 
11646d3ceb1dSskrll void
dino_wrm_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)11656d3ceb1dSskrll dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o,
11666d3ceb1dSskrll     const uint64_t *a, bus_size_t c)
11676d3ceb1dSskrll {
11686d3ceb1dSskrll 	panic("dino_wrm_8: not implemented");
11696d3ceb1dSskrll }
11706d3ceb1dSskrll 
11716d3ceb1dSskrll void
dino_rr_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t * a,bus_size_t c)11726d3ceb1dSskrll dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c)
11736d3ceb1dSskrll {
11746d3ceb1dSskrll 	volatile uint8_t *p;
11756d3ceb1dSskrll 
11766d3ceb1dSskrll 	h += o;
11776d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
11786d3ceb1dSskrll 		p = (volatile uint8_t *)h;
11796d3ceb1dSskrll 		while (c--)
11806d3ceb1dSskrll 			*a++ = *p++;
11816d3ceb1dSskrll 	} else {
11826d3ceb1dSskrll 		struct dino_softc *sc = v;
11836d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
11846d3ceb1dSskrll 
11856d3ceb1dSskrll 		for (; c--; h++) {
11866d3ceb1dSskrll 			r->pci_addr = h;
11876d3ceb1dSskrll 			p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
11886d3ceb1dSskrll 			*a++ = *p;
11896d3ceb1dSskrll 		}
11906d3ceb1dSskrll 	}
11916d3ceb1dSskrll }
11926d3ceb1dSskrll 
11936d3ceb1dSskrll void
dino_rr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)11946d3ceb1dSskrll dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c)
11956d3ceb1dSskrll {
11966d3ceb1dSskrll 	volatile uint16_t *p, data;
11976d3ceb1dSskrll 
11986d3ceb1dSskrll 	h += o;
11996d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
12006d3ceb1dSskrll 		p = (volatile uint16_t *)h;
12016d3ceb1dSskrll 		while (c--) {
12026d3ceb1dSskrll 			data = *p++;
12036d3ceb1dSskrll 			*a++ = le16toh(data);
12046d3ceb1dSskrll 		}
12056d3ceb1dSskrll 	} else {
12066d3ceb1dSskrll 		struct dino_softc *sc = v;
12076d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
12086d3ceb1dSskrll 
12096d3ceb1dSskrll 		for (; c--; h += 2) {
12106d3ceb1dSskrll 			r->pci_addr = h;
12116d3ceb1dSskrll 			p = (volatile uint16_t *)&r->pci_io_data;
12126d3ceb1dSskrll 			if (h & 2)
12136d3ceb1dSskrll 				p++;
12146d3ceb1dSskrll 			data = *p;
12156d3ceb1dSskrll 			*a++ = le16toh(data);
12166d3ceb1dSskrll 		}
12176d3ceb1dSskrll 	}
12186d3ceb1dSskrll }
12196d3ceb1dSskrll 
12206d3ceb1dSskrll void
dino_rr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)12216d3ceb1dSskrll dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c)
12226d3ceb1dSskrll {
12236d3ceb1dSskrll 	volatile uint32_t *p, data;
12246d3ceb1dSskrll 
12256d3ceb1dSskrll 	h += o;
12266d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
12276d3ceb1dSskrll 		p = (volatile uint32_t *)h;
12286d3ceb1dSskrll 		while (c--) {
12296d3ceb1dSskrll 			data = *p++;
12306d3ceb1dSskrll 			*a++ = le32toh(data);
12316d3ceb1dSskrll 		}
12326d3ceb1dSskrll 	} else {
12336d3ceb1dSskrll 		struct dino_softc *sc = v;
12346d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
12356d3ceb1dSskrll 
12366d3ceb1dSskrll 		for (; c--; h += 4) {
12376d3ceb1dSskrll 			r->pci_addr = h;
12386d3ceb1dSskrll 			data = r->pci_io_data;
12396d3ceb1dSskrll 			*a++ = le32toh(data);
12406d3ceb1dSskrll 		}
12416d3ceb1dSskrll 	}
12426d3ceb1dSskrll }
12436d3ceb1dSskrll 
12446d3ceb1dSskrll void
dino_rr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)12456d3ceb1dSskrll dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c)
12466d3ceb1dSskrll {
12476d3ceb1dSskrll 	panic("dino_rr_8: not implemented");
12486d3ceb1dSskrll }
12496d3ceb1dSskrll 
12506d3ceb1dSskrll void
dino_wr_1(void * v,bus_space_handle_t h,bus_size_t o,const uint8_t * a,bus_size_t c)12516d3ceb1dSskrll dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c)
12526d3ceb1dSskrll {
12536d3ceb1dSskrll 	volatile uint8_t *p;
12546d3ceb1dSskrll 
12556d3ceb1dSskrll 	h += o;
12566d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
12576d3ceb1dSskrll 		p = (volatile uint8_t *)h;
12586d3ceb1dSskrll 		while (c--)
12596d3ceb1dSskrll 			*p++ = *a++;
12606d3ceb1dSskrll 	} else {
12616d3ceb1dSskrll 		struct dino_softc *sc = v;
12626d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
12636d3ceb1dSskrll 
12646d3ceb1dSskrll 		for (; c--; h++) {
12656d3ceb1dSskrll 			r->pci_addr = h;
12666d3ceb1dSskrll 			p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
12676d3ceb1dSskrll 			*p = *a++;
12686d3ceb1dSskrll 		}
12696d3ceb1dSskrll 	}
12706d3ceb1dSskrll }
12716d3ceb1dSskrll 
12726d3ceb1dSskrll void
dino_wr_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)12736d3ceb1dSskrll dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c)
12746d3ceb1dSskrll {
12756d3ceb1dSskrll 	volatile uint16_t *p, data;
12766d3ceb1dSskrll 
12776d3ceb1dSskrll 	h += o;
12786d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
12796d3ceb1dSskrll 		p = (volatile uint16_t *)h;
12806d3ceb1dSskrll 		while (c--) {
12816d3ceb1dSskrll 			data = *a++;
12826d3ceb1dSskrll 			*p++ = htole16(data);
12836d3ceb1dSskrll 		}
12846d3ceb1dSskrll 	} else {
12856d3ceb1dSskrll 		struct dino_softc *sc = v;
12866d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
12876d3ceb1dSskrll 
12886d3ceb1dSskrll 		for (; c--; h += 2) {
12896d3ceb1dSskrll 			r->pci_addr = h;
12906d3ceb1dSskrll 			p = (volatile uint16_t *)&r->pci_io_data;
12916d3ceb1dSskrll 			if (h & 2)
12926d3ceb1dSskrll 				p++;
12936d3ceb1dSskrll 			data = *a++;
12946d3ceb1dSskrll 			*p = htole16(data);
12956d3ceb1dSskrll 		}
12966d3ceb1dSskrll 	}
12976d3ceb1dSskrll }
12986d3ceb1dSskrll 
12996d3ceb1dSskrll void
dino_wr_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)13006d3ceb1dSskrll dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c)
13016d3ceb1dSskrll {
13026d3ceb1dSskrll 	volatile uint32_t *p, data;
13036d3ceb1dSskrll 
13046d3ceb1dSskrll 	h += o;
13056d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
13066d3ceb1dSskrll 		p = (volatile uint32_t *)h;
13076d3ceb1dSskrll 		while (c--) {
13086d3ceb1dSskrll 			data = *a++;
13096d3ceb1dSskrll 			*p++ = htole32(data);
13106d3ceb1dSskrll 		}
13116d3ceb1dSskrll 	} else {
13126d3ceb1dSskrll 		struct dino_softc *sc = v;
13136d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
13146d3ceb1dSskrll 
13156d3ceb1dSskrll 		for (; c--; h += 4) {
13166d3ceb1dSskrll 			r->pci_addr = h;
13176d3ceb1dSskrll 			data = *a++;
13186d3ceb1dSskrll 			r->pci_io_data = htole32(data);
13196d3ceb1dSskrll 		}
13206d3ceb1dSskrll 	}
13216d3ceb1dSskrll }
13226d3ceb1dSskrll 
13236d3ceb1dSskrll void
dino_wr_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)13246d3ceb1dSskrll dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c)
13256d3ceb1dSskrll {
13266d3ceb1dSskrll 	panic("dino_wr_8: not implemented");
13276d3ceb1dSskrll }
13286d3ceb1dSskrll 
13296d3ceb1dSskrll void
dino_rrr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t * a,bus_size_t c)13306d3ceb1dSskrll dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o,
13316d3ceb1dSskrll     uint16_t *a, bus_size_t c)
13326d3ceb1dSskrll {
13336d3ceb1dSskrll 	volatile uint16_t *p;
13346d3ceb1dSskrll 
13356d3ceb1dSskrll 	h += o;
13366d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
13376d3ceb1dSskrll 		p = (volatile uint16_t *)h;
13386d3ceb1dSskrll 		while (c--)
13396d3ceb1dSskrll 			*a++ = *p++;
13406d3ceb1dSskrll 	} else {
13416d3ceb1dSskrll 		struct dino_softc *sc = v;
13426d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
13436d3ceb1dSskrll 
13446d3ceb1dSskrll 		for (; c--; h += 2) {
13456d3ceb1dSskrll 			r->pci_addr = h;
13466d3ceb1dSskrll 			p = (volatile uint16_t *)&r->pci_io_data;
13476d3ceb1dSskrll 			if (h & 2)
13486d3ceb1dSskrll 				p++;
13496d3ceb1dSskrll 			*a++ = *p;
13506d3ceb1dSskrll 		}
13516d3ceb1dSskrll 	}
13526d3ceb1dSskrll }
13536d3ceb1dSskrll 
13546d3ceb1dSskrll void
dino_rrr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t * a,bus_size_t c)13556d3ceb1dSskrll dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o,
13566d3ceb1dSskrll     uint32_t *a, bus_size_t c)
13576d3ceb1dSskrll {
13586d3ceb1dSskrll 	volatile uint32_t *p;
13596d3ceb1dSskrll 
13606d3ceb1dSskrll 	h += o;
13616d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
13626d3ceb1dSskrll 		p = (volatile uint32_t *)h;
13636d3ceb1dSskrll 		while (c--)
13646d3ceb1dSskrll 			*a++ = *p++;
13656d3ceb1dSskrll 	} else {
13666d3ceb1dSskrll 		struct dino_softc *sc = v;
13676d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
13686d3ceb1dSskrll 
13696d3ceb1dSskrll 		for (; c--; h += 4) {
13706d3ceb1dSskrll 			r->pci_addr = h;
13716d3ceb1dSskrll 			*a++ = r->pci_io_data;
13726d3ceb1dSskrll 		}
13736d3ceb1dSskrll 	}
13746d3ceb1dSskrll }
13756d3ceb1dSskrll 
13766d3ceb1dSskrll void
dino_rrr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t * a,bus_size_t c)13776d3ceb1dSskrll dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o,
13786d3ceb1dSskrll     uint64_t *a, bus_size_t c)
13796d3ceb1dSskrll {
13806d3ceb1dSskrll 	panic("dino_rrr_8: not implemented");
13816d3ceb1dSskrll }
13826d3ceb1dSskrll 
13836d3ceb1dSskrll void
dino_wrr_2(void * v,bus_space_handle_t h,bus_size_t o,const uint16_t * a,bus_size_t c)13846d3ceb1dSskrll dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o,
13856d3ceb1dSskrll     const uint16_t *a, bus_size_t c)
13866d3ceb1dSskrll {
13876d3ceb1dSskrll 	volatile uint16_t *p;
13886d3ceb1dSskrll 
13896d3ceb1dSskrll 	h += o;
13906d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
13916d3ceb1dSskrll 		p = (volatile uint16_t *)h;
13926d3ceb1dSskrll 		while (c--)
13936d3ceb1dSskrll 			*p++ = *a++;
13946d3ceb1dSskrll 	} else {
13956d3ceb1dSskrll 		struct dino_softc *sc = v;
13966d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
13976d3ceb1dSskrll 
13986d3ceb1dSskrll 		for (; c--; h += 2) {
13996d3ceb1dSskrll 			r->pci_addr = h;
14006d3ceb1dSskrll 			p = (volatile uint16_t *)&r->pci_io_data;
14016d3ceb1dSskrll 			if (h & 2)
14026d3ceb1dSskrll 				p++;
14036d3ceb1dSskrll 			*p = *a++;
14046d3ceb1dSskrll 		}
14056d3ceb1dSskrll 	}
14066d3ceb1dSskrll }
14076d3ceb1dSskrll 
14086d3ceb1dSskrll void
dino_wrr_4(void * v,bus_space_handle_t h,bus_size_t o,const uint32_t * a,bus_size_t c)14096d3ceb1dSskrll dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o,
14106d3ceb1dSskrll     const uint32_t *a, bus_size_t c)
14116d3ceb1dSskrll {
14126d3ceb1dSskrll 	volatile uint32_t *p;
14136d3ceb1dSskrll 
14146d3ceb1dSskrll 	c /= 4;
14156d3ceb1dSskrll 	h += o;
14166d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
14176d3ceb1dSskrll 		p = (volatile uint32_t *)h;
14186d3ceb1dSskrll 		while (c--)
14196d3ceb1dSskrll 			*p++ = *a++;
14206d3ceb1dSskrll 	} else {
14216d3ceb1dSskrll 		struct dino_softc *sc = v;
14226d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
14236d3ceb1dSskrll 
14246d3ceb1dSskrll 		for (; c--; h += 4) {
14256d3ceb1dSskrll 			r->pci_addr = h;
14266d3ceb1dSskrll 			r->pci_io_data = *a++;
14276d3ceb1dSskrll 		}
14286d3ceb1dSskrll 	}
14296d3ceb1dSskrll }
14306d3ceb1dSskrll 
14316d3ceb1dSskrll void
dino_wrr_8(void * v,bus_space_handle_t h,bus_size_t o,const uint64_t * a,bus_size_t c)14326d3ceb1dSskrll dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o,
14336d3ceb1dSskrll     const uint64_t *a, bus_size_t c)
14346d3ceb1dSskrll {
14356d3ceb1dSskrll 	panic("dino_wrr_8: not implemented");
14366d3ceb1dSskrll }
14376d3ceb1dSskrll 
14386d3ceb1dSskrll void
dino_sr_1(void * v,bus_space_handle_t h,bus_size_t o,uint8_t vv,bus_size_t c)14396d3ceb1dSskrll dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c)
14406d3ceb1dSskrll {
14416d3ceb1dSskrll 	volatile uint8_t *p;
14426d3ceb1dSskrll 
14436d3ceb1dSskrll 	h += o;
14446d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
14456d3ceb1dSskrll 		p = (volatile uint8_t *)h;
14466d3ceb1dSskrll 		while (c--)
14476d3ceb1dSskrll 			*p++ = vv;
14486d3ceb1dSskrll 	} else {
14496d3ceb1dSskrll 		struct dino_softc *sc = v;
14506d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
14516d3ceb1dSskrll 
14526d3ceb1dSskrll 		for (; c--; h++) {
14536d3ceb1dSskrll 			r->pci_addr = h;
14546d3ceb1dSskrll 			p = (volatile uint8_t *)&r->pci_io_data + (h & 3);
14556d3ceb1dSskrll 			*p = vv;
14566d3ceb1dSskrll 		}
14576d3ceb1dSskrll 	}
14586d3ceb1dSskrll }
14596d3ceb1dSskrll 
14606d3ceb1dSskrll void
dino_sr_2(void * v,bus_space_handle_t h,bus_size_t o,uint16_t vv,bus_size_t c)14616d3ceb1dSskrll dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c)
14626d3ceb1dSskrll {
14636d3ceb1dSskrll 	volatile uint16_t *p;
14646d3ceb1dSskrll 
14656d3ceb1dSskrll 	h += o;
14666d3ceb1dSskrll 	vv = htole16(vv);
14676d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
14686d3ceb1dSskrll 		p = (volatile uint16_t *)h;
14696d3ceb1dSskrll 		while (c--)
14706d3ceb1dSskrll 			*p++ = vv;
14716d3ceb1dSskrll 	} else {
14726d3ceb1dSskrll 		struct dino_softc *sc = v;
14736d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
14746d3ceb1dSskrll 
14756d3ceb1dSskrll 		for (; c--; h += 2) {
14766d3ceb1dSskrll 			r->pci_addr = h;
14776d3ceb1dSskrll 			p = (volatile uint16_t *)&r->pci_io_data;
14786d3ceb1dSskrll 			if (h & 2)
14796d3ceb1dSskrll 				p++;
14806d3ceb1dSskrll 			*p = vv;
14816d3ceb1dSskrll 		}
14826d3ceb1dSskrll 	}
14836d3ceb1dSskrll }
14846d3ceb1dSskrll 
14856d3ceb1dSskrll void
dino_sr_4(void * v,bus_space_handle_t h,bus_size_t o,uint32_t vv,bus_size_t c)14866d3ceb1dSskrll dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c)
14876d3ceb1dSskrll {
14886d3ceb1dSskrll 	volatile uint32_t *p;
14896d3ceb1dSskrll 
14906d3ceb1dSskrll 	h += o;
14916d3ceb1dSskrll 	vv = htole32(vv);
14926d3ceb1dSskrll 	if (h & HPPA_IOSPACE) {
14936d3ceb1dSskrll 		p = (volatile uint32_t *)h;
14946d3ceb1dSskrll 		while (c--)
14956d3ceb1dSskrll 			*p++ = vv;
14966d3ceb1dSskrll 	} else {
14976d3ceb1dSskrll 		struct dino_softc *sc = v;
14986d3ceb1dSskrll 		volatile struct dino_regs *r = sc->sc_regs;
14996d3ceb1dSskrll 
15006d3ceb1dSskrll 		for (; c--; h += 4) {
15016d3ceb1dSskrll 			r->pci_addr = h;
15026d3ceb1dSskrll 			r->pci_io_data = vv;
15036d3ceb1dSskrll 		}
15046d3ceb1dSskrll 	}
15056d3ceb1dSskrll }
15066d3ceb1dSskrll 
15076d3ceb1dSskrll void
dino_sr_8(void * v,bus_space_handle_t h,bus_size_t o,uint64_t vv,bus_size_t c)15086d3ceb1dSskrll dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c)
15096d3ceb1dSskrll {
15106d3ceb1dSskrll 	panic("dino_sr_8: not implemented");
15116d3ceb1dSskrll }
15126d3ceb1dSskrll 
15136d3ceb1dSskrll void
dino_cp_1(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)15146d3ceb1dSskrll dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1,
15156d3ceb1dSskrll 	  bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
15166d3ceb1dSskrll {
15176d3ceb1dSskrll 	while (c--)
15186d3ceb1dSskrll 		dino_w1(v, h1, o1++, dino_r1(v, h2, o2++));
15196d3ceb1dSskrll }
15206d3ceb1dSskrll 
15216d3ceb1dSskrll void
dino_cp_2(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)15226d3ceb1dSskrll dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1,
15236d3ceb1dSskrll 	  bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
15246d3ceb1dSskrll {
15256d3ceb1dSskrll 	while (c--) {
15266d3ceb1dSskrll 		dino_w2(v, h1, o1, dino_r2(v, h2, o2));
15276d3ceb1dSskrll 		o1 += 2;
15286d3ceb1dSskrll 		o2 += 2;
15296d3ceb1dSskrll 	}
15306d3ceb1dSskrll }
15316d3ceb1dSskrll 
15326d3ceb1dSskrll void
dino_cp_4(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)15336d3ceb1dSskrll dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1,
15346d3ceb1dSskrll 	  bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
15356d3ceb1dSskrll {
15366d3ceb1dSskrll 	while (c--) {
15376d3ceb1dSskrll 		dino_w4(v, h1, o1, dino_r4(v, h2, o2));
15386d3ceb1dSskrll 		o1 += 4;
15396d3ceb1dSskrll 		o2 += 4;
15406d3ceb1dSskrll 	}
15416d3ceb1dSskrll }
15426d3ceb1dSskrll 
15436d3ceb1dSskrll void
dino_cp_8(void * v,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,bus_size_t c)15446d3ceb1dSskrll dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1,
15456d3ceb1dSskrll 	  bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
15466d3ceb1dSskrll {
15476d3ceb1dSskrll 	while (c--) {
15486d3ceb1dSskrll 		dino_w8(v, h1, o1, dino_r8(v, h2, o2));
15496d3ceb1dSskrll 		o1 += 8;
15506d3ceb1dSskrll 		o2 += 8;
15516d3ceb1dSskrll 	}
15526d3ceb1dSskrll }
15536d3ceb1dSskrll 
15546d3ceb1dSskrll 
15556d3ceb1dSskrll const struct hppa_bus_space_tag dino_iomemt = {
15566d3ceb1dSskrll 	NULL,
15576d3ceb1dSskrll 
15586d3ceb1dSskrll 	NULL, dino_unmap, dino_subregion, NULL, dino_free,
15596d3ceb1dSskrll 	dino_barrier, dino_vaddr, dino_mmap,
15606d3ceb1dSskrll 	dino_r1,    dino_r2,    dino_r4,    dino_r8,
1561*dbeed521Smacallan 		    dino_rs2,   dino_rs4,   dino_rs8,
15626d3ceb1dSskrll 	dino_w1,    dino_w2,    dino_w4,    dino_w8,
1563*dbeed521Smacallan 	            dino_ws2,   dino_ws4,   dino_ws8,
15646d3ceb1dSskrll 	dino_rm_1,  dino_rm_2,  dino_rm_4,  dino_rm_8,
15656d3ceb1dSskrll 	dino_wm_1,  dino_wm_2,  dino_wm_4,  dino_wm_8,
15666d3ceb1dSskrll 	dino_sm_1,  dino_sm_2,  dino_sm_4,  dino_sm_8,
15676d3ceb1dSskrll 	            dino_rrm_2, dino_rrm_4, dino_rrm_8,
15686d3ceb1dSskrll 	            dino_wrm_2, dino_wrm_4, dino_wrm_8,
15696d3ceb1dSskrll 	dino_rr_1,  dino_rr_2,  dino_rr_4,  dino_rr_8,
15706d3ceb1dSskrll 	dino_wr_1,  dino_wr_2,  dino_wr_4,  dino_wr_8,
15716d3ceb1dSskrll 	            dino_rrr_2, dino_rrr_4, dino_rrr_8,
15726d3ceb1dSskrll 	            dino_wrr_2, dino_wrr_4, dino_wrr_8,
15736d3ceb1dSskrll 	dino_sr_1,  dino_sr_2,  dino_sr_4,  dino_sr_8,
15746d3ceb1dSskrll 	dino_cp_1,  dino_cp_2,  dino_cp_4,  dino_cp_8
15756d3ceb1dSskrll };
15766d3ceb1dSskrll 
15776d3ceb1dSskrll int
dino_dmamap_create(void * v,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)15786d3ceb1dSskrll dino_dmamap_create(void *v, bus_size_t size, int nsegments,
15796d3ceb1dSskrll     bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp)
15806d3ceb1dSskrll {
15816d3ceb1dSskrll 	struct dino_softc *sc = v;
15826d3ceb1dSskrll 
15836d3ceb1dSskrll 	/* TODO check the addresses, boundary, enable dma */
15846d3ceb1dSskrll 
15856d3ceb1dSskrll 	return bus_dmamap_create(sc->sc_dmat, size, nsegments,
15866d3ceb1dSskrll 	    maxsegsz, boundary, flags, dmamp);
15876d3ceb1dSskrll }
15886d3ceb1dSskrll 
15896d3ceb1dSskrll void
dino_dmamap_destroy(void * v,bus_dmamap_t map)15906d3ceb1dSskrll dino_dmamap_destroy(void *v, bus_dmamap_t map)
15916d3ceb1dSskrll {
15926d3ceb1dSskrll 	struct dino_softc *sc = v;
15936d3ceb1dSskrll 
15946d3ceb1dSskrll 	bus_dmamap_destroy(sc->sc_dmat, map);
15956d3ceb1dSskrll }
15966d3ceb1dSskrll 
15976d3ceb1dSskrll int
dino_dmamap_load(void * v,bus_dmamap_t map,void * addr,bus_size_t size,struct proc * p,int flags)15986d3ceb1dSskrll dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size,
15996d3ceb1dSskrll     struct proc *p, int flags)
16006d3ceb1dSskrll {
16016d3ceb1dSskrll 	struct dino_softc *sc = v;
16026d3ceb1dSskrll 
16036d3ceb1dSskrll 	return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags);
16046d3ceb1dSskrll }
16056d3ceb1dSskrll 
16066d3ceb1dSskrll int
dino_dmamap_load_mbuf(void * v,bus_dmamap_t map,struct mbuf * m,int flags)16076d3ceb1dSskrll dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags)
16086d3ceb1dSskrll {
16096d3ceb1dSskrll 	struct dino_softc *sc = v;
16106d3ceb1dSskrll 
16116d3ceb1dSskrll 	return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags);
16126d3ceb1dSskrll }
16136d3ceb1dSskrll 
16146d3ceb1dSskrll int
dino_dmamap_load_uio(void * v,bus_dmamap_t map,struct uio * uio,int flags)16156d3ceb1dSskrll dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags)
16166d3ceb1dSskrll {
16176d3ceb1dSskrll 	struct dino_softc *sc = v;
16186d3ceb1dSskrll 
16196d3ceb1dSskrll 	return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags);
16206d3ceb1dSskrll }
16216d3ceb1dSskrll 
16226d3ceb1dSskrll int
dino_dmamap_load_raw(void * v,bus_dmamap_t map,bus_dma_segment_t * segs,int nsegs,bus_size_t size,int flags)16236d3ceb1dSskrll dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs,
16246d3ceb1dSskrll     int nsegs, bus_size_t size, int flags)
16256d3ceb1dSskrll {
16266d3ceb1dSskrll 	struct dino_softc *sc = v;
16276d3ceb1dSskrll 
16286d3ceb1dSskrll 	return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags);
16296d3ceb1dSskrll }
16306d3ceb1dSskrll 
16316d3ceb1dSskrll void
dino_dmamap_unload(void * v,bus_dmamap_t map)16326d3ceb1dSskrll dino_dmamap_unload(void *v, bus_dmamap_t map)
16336d3ceb1dSskrll {
16346d3ceb1dSskrll 	struct dino_softc *sc = v;
16356d3ceb1dSskrll 
16366d3ceb1dSskrll 	bus_dmamap_unload(sc->sc_dmat, map);
16376d3ceb1dSskrll }
16386d3ceb1dSskrll 
16396d3ceb1dSskrll void
dino_dmamap_sync(void * v,bus_dmamap_t map,bus_addr_t off,bus_size_t len,int ops)16406d3ceb1dSskrll dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off,
16416d3ceb1dSskrll     bus_size_t len, int ops)
16426d3ceb1dSskrll {
16436d3ceb1dSskrll 	struct dino_softc *sc = v;
16446d3ceb1dSskrll 
16456d3ceb1dSskrll 	return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops);
16466d3ceb1dSskrll }
16476d3ceb1dSskrll 
16486d3ceb1dSskrll int
dino_dmamem_alloc(void * v,bus_size_t size,bus_size_t alignment,bus_size_t boundary,bus_dma_segment_t * segs,int nsegs,int * rsegs,int flags)16496d3ceb1dSskrll dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment,
16506d3ceb1dSskrll     bus_size_t boundary, bus_dma_segment_t *segs,
16516d3ceb1dSskrll     int nsegs, int *rsegs, int flags)
16526d3ceb1dSskrll {
16536d3ceb1dSskrll 	struct dino_softc *sc = v;
16546d3ceb1dSskrll 
16556d3ceb1dSskrll 	return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary,
16566d3ceb1dSskrll 	    segs, nsegs, rsegs, flags);
16576d3ceb1dSskrll }
16586d3ceb1dSskrll 
16596d3ceb1dSskrll void
dino_dmamem_free(void * v,bus_dma_segment_t * segs,int nsegs)16606d3ceb1dSskrll dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs)
16616d3ceb1dSskrll {
16626d3ceb1dSskrll 	struct dino_softc *sc = v;
16636d3ceb1dSskrll 
16646d3ceb1dSskrll 	bus_dmamem_free(sc->sc_dmat, segs, nsegs);
16656d3ceb1dSskrll }
16666d3ceb1dSskrll 
16676d3ceb1dSskrll int
dino_dmamem_map(void * v,bus_dma_segment_t * segs,int nsegs,size_t size,void ** kvap,int flags)16686d3ceb1dSskrll dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size,
16696d3ceb1dSskrll     void **kvap, int flags)
16706d3ceb1dSskrll {
16716d3ceb1dSskrll 	struct dino_softc *sc = v;
16726d3ceb1dSskrll 
16736d3ceb1dSskrll 	return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags);
16746d3ceb1dSskrll }
16756d3ceb1dSskrll 
16766d3ceb1dSskrll void
dino_dmamem_unmap(void * v,void * kva,size_t size)16776d3ceb1dSskrll dino_dmamem_unmap(void *v, void *kva, size_t size)
16786d3ceb1dSskrll {
16796d3ceb1dSskrll 	struct dino_softc *sc = v;
16806d3ceb1dSskrll 
16816d3ceb1dSskrll 	bus_dmamem_unmap(sc->sc_dmat, kva, size);
16826d3ceb1dSskrll }
16836d3ceb1dSskrll 
16846d3ceb1dSskrll paddr_t
dino_dmamem_mmap(void * v,bus_dma_segment_t * segs,int nsegs,off_t off,int prot,int flags)16856d3ceb1dSskrll dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off,
16866d3ceb1dSskrll     int prot, int flags)
16876d3ceb1dSskrll {
16886d3ceb1dSskrll 	struct dino_softc *sc = v;
16896d3ceb1dSskrll 
16906d3ceb1dSskrll 	return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags);
16916d3ceb1dSskrll }
16926d3ceb1dSskrll 
16936d3ceb1dSskrll const struct hppa_bus_dma_tag dino_dmat = {
16946d3ceb1dSskrll 	NULL,
16956d3ceb1dSskrll 	dino_dmamap_create, dino_dmamap_destroy,
16966d3ceb1dSskrll 	dino_dmamap_load, dino_dmamap_load_mbuf,
16976d3ceb1dSskrll 	dino_dmamap_load_uio, dino_dmamap_load_raw,
16986d3ceb1dSskrll 	dino_dmamap_unload, dino_dmamap_sync,
16996d3ceb1dSskrll 
17006d3ceb1dSskrll 	dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map,
17016d3ceb1dSskrll 	dino_dmamem_unmap, dino_dmamem_mmap
17026d3ceb1dSskrll };
17036d3ceb1dSskrll 
17046d3ceb1dSskrll const struct hppa_pci_chipset_tag dino_pc = {
170555f4a551Sskrll 	.pc_attach_hook = dino_attach_hook,
170655f4a551Sskrll 	.pc_bus_maxdevs = dino_maxdevs,
170755f4a551Sskrll 	.pc_make_tag = dino_make_tag,
170855f4a551Sskrll 	.pc_decompose_tag = dino_decompose_tag,
170955f4a551Sskrll 	.pc_conf_read = dino_conf_read,
171055f4a551Sskrll 	.pc_conf_write = dino_conf_write,
171155f4a551Sskrll 	.pc_intr_map = dino_intr_map,
171255f4a551Sskrll 	.pc_intr_string = dino_intr_string,
171355f4a551Sskrll 	.pc_intr_establish = dino_intr_establish,
171455f4a551Sskrll 	.pc_intr_disestablish = dino_intr_disestablish,
17156d3ceb1dSskrll #if NCARDBUS > 0
171655f4a551Sskrll 	.pc_alloc_parent = dino_alloc_parent,
17176d3ceb1dSskrll #endif
17186d3ceb1dSskrll };
17196d3ceb1dSskrll 
17206d3ceb1dSskrll int
dinomatch(device_t parent,cfdata_t cfdata,void * aux)17216d3ceb1dSskrll dinomatch(device_t parent, cfdata_t cfdata, void *aux)
17226d3ceb1dSskrll {
17236d3ceb1dSskrll 	struct confargs *ca = aux;
17246d3ceb1dSskrll 
17256d3ceb1dSskrll 	/* there will be only one */
17266d3ceb1dSskrll 	if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE ||
17276d3ceb1dSskrll 	    ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO)
17286d3ceb1dSskrll 		return 0;
17296d3ceb1dSskrll 
17306d3ceb1dSskrll 	/* do not match on the elroy family */
17316d3ceb1dSskrll 	if (ca->ca_type.iodc_model == 0x78)
17326d3ceb1dSskrll 		return 0;
17336d3ceb1dSskrll 
17346d3ceb1dSskrll 	return 1;
17356d3ceb1dSskrll }
17366d3ceb1dSskrll 
17376d3ceb1dSskrll void
dinoattach(device_t parent,device_t self,void * aux)17386d3ceb1dSskrll dinoattach(device_t parent, device_t self, void *aux)
17396d3ceb1dSskrll {
17406d3ceb1dSskrll 	struct dino_softc *sc = device_private(self);
17416d3ceb1dSskrll 	struct confargs *ca = (struct confargs *)aux, nca;
17426d3ceb1dSskrll 	struct pcibus_attach_args pba;
17436d3ceb1dSskrll 	volatile struct dino_regs *r;
17446d3ceb1dSskrll 	struct cpu_info *ci = &cpus[0];
17456d3ceb1dSskrll 	const char *p = NULL;
17466d3ceb1dSskrll 	int s, ver;
17476d3ceb1dSskrll 
17486d3ceb1dSskrll 	sc->sc_dv = self;
17496d3ceb1dSskrll 	sc->sc_bt = ca->ca_iot;
17506d3ceb1dSskrll 	sc->sc_dmat = ca->ca_dmatag;
17516d3ceb1dSskrll 
17526d3ceb1dSskrll 	ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq);
17536d3ceb1dSskrll 	if (ca->ca_irq == HPPACF_IRQ_UNDEF) {
17546d3ceb1dSskrll 		aprint_error_dev(self, ": can't allocate interrupt");
17556d3ceb1dSskrll 		return;
17566d3ceb1dSskrll 	}
17576d3ceb1dSskrll 
17586d3ceb1dSskrll 	if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) {
17596d3ceb1dSskrll 		aprint_error(": can't map space\n");
17606d3ceb1dSskrll 		return;
17616d3ceb1dSskrll 	}
17626d3ceb1dSskrll 
17636d3ceb1dSskrll 	sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh;
1764*dbeed521Smacallan 
17656d3ceb1dSskrll #ifdef trust_the_firmware_to_proper_initialize_everything
17666d3ceb1dSskrll 	r->io_addr_en = 0;
17676d3ceb1dSskrll 	r->io_control = 0x80;
17686d3ceb1dSskrll 	r->pamr = 0;
17696d3ceb1dSskrll 	r->papr = 0;
17706d3ceb1dSskrll 	r->io_fbb_en |= 1;
17716d3ceb1dSskrll 	r->damode = 0;
17726d3ceb1dSskrll 	r->gmask &= ~1; /* allow GSC bus req */
17736d3ceb1dSskrll 	r->pciror = 0;
17746d3ceb1dSskrll 	r->pciwor = 0;
17756d3ceb1dSskrll 	r->brdg_feat = 0xc0000000;
17766d3ceb1dSskrll #endif
17776d3ceb1dSskrll 
17786d3ceb1dSskrll 	snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname),
17796d3ceb1dSskrll 	    "%s_io", device_xname(self));
178069a3e9b7Schs 	sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff,
178169a3e9b7Schs 	    NULL, 0, EX_WAITOK | EX_MALLOCOK);
17826d3ceb1dSskrll 
17836d3ceb1dSskrll 	/* interrupts guts */
17846d3ceb1dSskrll 	s = splhigh();
17856d3ceb1dSskrll 	r->icr = 0;
17866d3ceb1dSskrll 	r->imr = 0;
1787fc85ec4fSskrll 	(void)r->irr0;
17886d3ceb1dSskrll 	r->iar0 = ci->ci_hpa | (31 - ca->ca_irq);
17896d3ceb1dSskrll 	splx(s);
17906d3ceb1dSskrll 	/* Establish the interrupt register. */
17916d3ceb1dSskrll 	hppa_interrupt_register_establish(ci, &sc->sc_ir);
17926d3ceb1dSskrll 	sc->sc_ir.ir_name = device_xname(self);
17936d3ceb1dSskrll 	sc->sc_ir.ir_mask = &r->imr;
17946d3ceb1dSskrll 	sc->sc_ir.ir_req = &r->irr0;
17956d3ceb1dSskrll 	sc->sc_ir.ir_level = &r->ilr;
17966d3ceb1dSskrll 	/* Add the I/O interrupt register. */
17976d3ceb1dSskrll 
17986d3ceb1dSskrll 	sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir,
17996d3ceb1dSskrll 	    &ci->ci_ir, ca->ca_irq);
18006d3ceb1dSskrll 
18016d3ceb1dSskrll 	/* TODO establish the bus error interrupt */
18026d3ceb1dSskrll 
18036d3ceb1dSskrll 	ver = ca->ca_type.iodc_revision;
18046d3ceb1dSskrll 	switch ((ca->ca_type.iodc_model << 4) |
18056d3ceb1dSskrll 	    (ca->ca_type.iodc_revision >> 4)) {
18066d3ceb1dSskrll 	case 0x05d:
18076d3ceb1dSskrll 		p = "Dino (card)";	/* j2240 */
18086d3ceb1dSskrll 		/* FALLTHROUGH */
18096d3ceb1dSskrll 	case 0x680:
18106d3ceb1dSskrll 		if (!p)
18116d3ceb1dSskrll 			p = "Dino";
18126d3ceb1dSskrll 		switch (ver & 0xf) {
18136d3ceb1dSskrll 		case 0:	ver = 0x20;	break;
18146d3ceb1dSskrll 		case 1:	ver = 0x21;	break;
18156d3ceb1dSskrll 		case 2:	ver = 0x30;	break;
18166d3ceb1dSskrll 		case 3:	ver = 0x31;	break;
18176d3ceb1dSskrll 		}
18186d3ceb1dSskrll 		break;
18196d3ceb1dSskrll 
18206d3ceb1dSskrll 	case 0x682:
18216d3ceb1dSskrll 		p = "Cujo";
18226d3ceb1dSskrll 		switch (ver & 0xf) {
18236d3ceb1dSskrll 		case 0:	ver = 0x10;	break;
18246d3ceb1dSskrll 		case 1:	ver = 0x20;	break;
18256d3ceb1dSskrll 		}
18266d3ceb1dSskrll 		break;
18276d3ceb1dSskrll 
18286d3ceb1dSskrll 	default:
18296d3ceb1dSskrll 		p = "Mojo";
18306d3ceb1dSskrll 		break;
18316d3ceb1dSskrll 	}
18326d3ceb1dSskrll 
18336d3ceb1dSskrll 	sc->sc_ver = ver;
18346d3ceb1dSskrll 	aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf);
18356d3ceb1dSskrll 
18366d3ceb1dSskrll 	sc->sc_iot = dino_iomemt;
18376d3ceb1dSskrll 	sc->sc_iot.hbt_cookie = sc;
18386d3ceb1dSskrll 	sc->sc_iot.hbt_map = dino_iomap;
18396d3ceb1dSskrll 	sc->sc_iot.hbt_alloc = dino_ioalloc;
18406d3ceb1dSskrll 	sc->sc_memt = dino_iomemt;
18416d3ceb1dSskrll 	sc->sc_memt.hbt_cookie = sc;
18426d3ceb1dSskrll 	sc->sc_memt.hbt_map = dino_memmap;
18436d3ceb1dSskrll 	sc->sc_memt.hbt_alloc = dino_memalloc;
18446d3ceb1dSskrll 	sc->sc_pc = dino_pc;
18456d3ceb1dSskrll 	sc->sc_pc._cookie = sc;
18466d3ceb1dSskrll 	sc->sc_dmatag = dino_dmat;
18476d3ceb1dSskrll 	sc->sc_dmatag._cookie = sc;
18486d3ceb1dSskrll 
18496d3ceb1dSskrll 	/* scan for ps2 kbd/ms, serial, and flying toasters */
18506d3ceb1dSskrll 	nca = *ca;
18516d3ceb1dSskrll 
18526d3ceb1dSskrll 	nca.ca_hpabase = 0;
18536d3ceb1dSskrll 	nca.ca_nmodules = MAXMODBUS;
18546d3ceb1dSskrll 	pdc_scanbus(self, &nca, dino_callback);
18556d3ceb1dSskrll 
18566d3ceb1dSskrll 	memset(&pba, 0, sizeof(pba));
18576d3ceb1dSskrll 	pba.pba_iot = &sc->sc_iot;
18586d3ceb1dSskrll 	pba.pba_memt = &sc->sc_memt;
18596d3ceb1dSskrll 	pba.pba_dmat = &sc->sc_dmatag;
18606d3ceb1dSskrll 	pba.pba_pc = &sc->sc_pc;
18616d3ceb1dSskrll 	pba.pba_bus = 0;
18626d3ceb1dSskrll 	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
18632685996bSthorpej 	config_found(self, &pba, pcibusprint,
1864c7fb772bSthorpej 	    CFARGS(.iattr = "pcibus"));
18656d3ceb1dSskrll }
18666d3ceb1dSskrll 
18676d3ceb1dSskrll static device_t
dino_callback(device_t self,struct confargs * ca)18686d3ceb1dSskrll dino_callback(device_t self, struct confargs *ca)
18696d3ceb1dSskrll {
18702685996bSthorpej 	return config_found(self, ca, mbprint,
1871c7fb772bSthorpej 	    CFARGS(.submatch = mbsubmatch,
1872c7fb772bSthorpej 		   .iattr = "gedoens"));
18736d3ceb1dSskrll }
1874