1*5004b778Sgreg /* 2*5004b778Sgreg * Copyright (c) 2001, 2002 Greg Hughes. All rights reserved. 3*5004b778Sgreg * Copyright (c) 1999 PocketBSD Project. All rights reserved. 4*5004b778Sgreg * 5*5004b778Sgreg * Redistribution and use in source and binary forms, with or without 6*5004b778Sgreg * modification, are permitted provided that the following conditions 7*5004b778Sgreg * are met: 8*5004b778Sgreg * 1. Redistributions of source code must retain the above copyright 9*5004b778Sgreg * notice, this list of conditions and the following disclaimer. 10*5004b778Sgreg * 2. Redistributions in binary form must reproduce the above copyright 11*5004b778Sgreg * notice, this list of conditions and the following disclaimer in the 12*5004b778Sgreg * documentation and/or other materials provided with the distribution. 13*5004b778Sgreg * 14*5004b778Sgreg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15*5004b778Sgreg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16*5004b778Sgreg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17*5004b778Sgreg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18*5004b778Sgreg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19*5004b778Sgreg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20*5004b778Sgreg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*5004b778Sgreg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22*5004b778Sgreg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23*5004b778Sgreg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24*5004b778Sgreg * SUCH DAMAGE. 25*5004b778Sgreg */ 26*5004b778Sgreg 27*5004b778Sgreg /* 28*5004b778Sgreg * DSIU (debug serial interface unit) register definitions 29*5004b778Sgreg */ 30*5004b778Sgreg 31*5004b778Sgreg /* Port Change Register */ 32*5004b778Sgreg #define DSIUPORT_REG_W 0x00 33*5004b778Sgreg #define DSIUPORT_CDDIN (1 << 3) 34*5004b778Sgreg #define DSIUPORT_CDDOUT (1 << 2) 35*5004b778Sgreg #define DSIUPORT_CDRTS (1 << 1) 36*5004b778Sgreg #define DSIUPORT_CDCTS (1 << 0) 37*5004b778Sgreg 38*5004b778Sgreg /* Modem Control Register */ 39*5004b778Sgreg #define DSIUMODEM_REG_W 0x02 40*5004b778Sgreg #define DSIUMODEM_DRTS (1 << 1) 41*5004b778Sgreg #define DSIUMODEM_DCTS (1 << 0) 42*5004b778Sgreg 43*5004b778Sgreg /* Asynchronous Mode 0 Register */ 44*5004b778Sgreg #define DSIUASIM00_REG_W 0x04 45*5004b778Sgreg #define DSIUASIM00_RXE0 (1 << 6) 46*5004b778Sgreg #define DSIUASIM00_PS0_MASK (3 << 4) 47*5004b778Sgreg #define DSIUASIM00_PS00 (1 << 4) 48*5004b778Sgreg #define DSIUASIM00_PS01 (1 << 5) 49*5004b778Sgreg #define DSIUASIM00_CL0 (1 << 3) 50*5004b778Sgreg #define DSIUASIM00_SL0 (1 << 2) 51*5004b778Sgreg 52*5004b778Sgreg /* Asynchronous Mode 1 Register */ 53*5004b778Sgreg #define DSIUASIM01_REG_W 0x06 54*5004b778Sgreg #define DSIUASIM01_EBS0 (1 << 0) 55*5004b778Sgreg 56*5004b778Sgreg /* Recceive Buffer Register (Extended) */ 57*5004b778Sgreg #define DSIURXB0R_REG_W 0x08 58*5004b778Sgreg #define DSIURXB0R_RXB0_MASK (0x1FF << 0) 59*5004b778Sgreg 60*5004b778Sgreg /* Receive Buffer Register */ 61*5004b778Sgreg #define DSIURXB0L_REG_W 0x0A 62*5004b778Sgreg #define DSIURXB0L_RXB0L_MASK (0xFF << 0) 63*5004b778Sgreg 64*5004b778Sgreg /* Transmit Data Register (Extended) */ 65*5004b778Sgreg #define DSIUTXS0R_REG_W 0x0C 66*5004b778Sgreg #define DSIUTXS0R_TXS0_MASK (0x1FF << 0) 67*5004b778Sgreg 68*5004b778Sgreg /* Transmit Data Register */ 69*5004b778Sgreg #define DSIUTXS0L_REG_W 0x0E 70*5004b778Sgreg #define DSIUTXS0L_TXS0L_MASK (0xFF << 0) 71*5004b778Sgreg 72*5004b778Sgreg /* Status Register */ 73*5004b778Sgreg #define DSIUASIS0_REG_W 0x10 74*5004b778Sgreg #define DSIUASIS0_SOT0 (1 << 7) 75*5004b778Sgreg #define DSIUASIS0_PE0 (1 << 2) 76*5004b778Sgreg #define DSIUASIS0_FE0 (1 << 1) 77*5004b778Sgreg #define DSIUASIS0_OVE0 (1 << 0) 78*5004b778Sgreg 79*5004b778Sgreg /* Debug SIU Interrupt Register */ 80*5004b778Sgreg #define DSIUINTR0_REG_W 0x12 81*5004b778Sgreg #define DSIUINTR0_INTDCD (1 << 3) 82*5004b778Sgreg #define DSIUINTR0_INTSER0 (1 << 2) 83*5004b778Sgreg #define DSIUINTR0_INTSR0 (1 << 1) 84*5004b778Sgreg #define DSIUINTR0_INTST0 (1 << 0) 85*5004b778Sgreg 86*5004b778Sgreg /* Baud rate Generator Prescaler Mode Register */ 87*5004b778Sgreg #define DSIUBPRM0_REG_W 0x16 88*5004b778Sgreg #define DSIUBPRM0_BRCE0 (1 << 7) 89*5004b778Sgreg #define DSIUBPRM0_BPR0_MASK (7 << 0) 90*5004b778Sgreg #define DSIUBPRM0_BPR00 (1 << 0) 91*5004b778Sgreg #define DSIUBPRM0_BPR01 (1 << 1) 92*5004b778Sgreg #define DSIUBPRM0_BPR02 (1 << 2) 93*5004b778Sgreg 94*5004b778Sgreg /* Debug SIU Reset Register */ 95*5004b778Sgreg #define DSIURESET_REG_W 0x18 96*5004b778Sgreg #define DSIURESET_DSIURST (1 << 0) 97