1*fddeb95fShamajima /* $NetBSD: vraiureg.h,v 1.1 2002/03/23 09:02:02 hamajima Exp $ */ 2*fddeb95fShamajima 3*fddeb95fShamajima /* 4*fddeb95fShamajima * Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved. 5*fddeb95fShamajima * 6*fddeb95fShamajima * Redistribution and use in source and binary forms, with or without 7*fddeb95fShamajima * modification, are permitted provided that the following conditions 8*fddeb95fShamajima * are met: 9*fddeb95fShamajima * 1. Redistributions of source code must retain the above copyright 10*fddeb95fShamajima * notice, this list of conditions and the following disclaimer. 11*fddeb95fShamajima * 2. Redistributions in binary form must reproduce the above copyright 12*fddeb95fShamajima * notice, this list of conditions and the following disclaimer in the 13*fddeb95fShamajima * documentation and/or other materials provided with the distribution. 14*fddeb95fShamajima * 15*fddeb95fShamajima * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*fddeb95fShamajima * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*fddeb95fShamajima * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*fddeb95fShamajima * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*fddeb95fShamajima * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*fddeb95fShamajima * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*fddeb95fShamajima * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*fddeb95fShamajima * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*fddeb95fShamajima * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*fddeb95fShamajima * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*fddeb95fShamajima * SUCH DAMAGE. 26*fddeb95fShamajima */ 27*fddeb95fShamajima 28*fddeb95fShamajima /* 29*fddeb95fShamajima * AIU (Audio Interface Unit) Registers definitions. 30*fddeb95fShamajima */ 31*fddeb95fShamajima 32*fddeb95fShamajima #define MDMADAT_REG_W 0x000 /* Mic DMA Data Register (10bit) */ 33*fddeb95fShamajima 34*fddeb95fShamajima #define SDMADAT_REG_W 0x002 /* Speaker DMA Data Register (10bit) */ 35*fddeb95fShamajima 36*fddeb95fShamajima #define SODATA_REG_W 0x006 /* Speaker Output Data Register (10bit) */ 37*fddeb95fShamajima 38*fddeb95fShamajima #define SCNT_REG_W 0x008 /* Speaker Control Register */ 39*fddeb95fShamajima #define DAENAIU (1<<15) /* D/A Enable */ 40*fddeb95fShamajima #define SSTATE (1<<3) /* Speaker Status */ 41*fddeb95fShamajima #define SSTOPEN (1<<1) /* Speaker Stop End 42*fddeb95fShamajima (1: 1 page, 0: 2 page) */ 43*fddeb95fShamajima 44*fddeb95fShamajima #define SCNVR_REG_W 0x00a /* Speaker Converter Rate Register */ 45*fddeb95fShamajima #define SPS8000 (4) /* 8k sps */ 46*fddeb95fShamajima #define SPS44100 (2) /* 44.1k sps */ 47*fddeb95fShamajima #define SPS22050 (1) /* 22.05k sps */ 48*fddeb95fShamajima #define SPS11025 (0) /* 11.025k sps */ 49*fddeb95fShamajima 50*fddeb95fShamajima #define MIDAT_REG_W 0x010 /* Mic Input Data Register (10bit) */ 51*fddeb95fShamajima 52*fddeb95fShamajima #define MCNT_REG_W 0x012 /* Mic Control Register */ 53*fddeb95fShamajima #define ADENAIU (1<<15) /* A/D Enable */ 54*fddeb95fShamajima #define MSTATE (1<<3) /* Mic Status */ 55*fddeb95fShamajima #define MSTOPEN (1<<1) /* Mic Stop End 56*fddeb95fShamajima (1: 1 page, 0: 2 page) */ 57*fddeb95fShamajima #define ADREQAIU (1) /* A/D Request */ 58*fddeb95fShamajima 59*fddeb95fShamajima #define MCNVR_REG_W 0x014 /* Mic Converter Rate Register */ 60*fddeb95fShamajima /* same SCNVR_REG_W(0x00a) 61*fddeb95fShamajima #define SPS8000 (4) 62*fddeb95fShamajima #define SPS44100 (2) 63*fddeb95fShamajima #define SPS22050 (1) 64*fddeb95fShamajima #define SPS11025 (0) 65*fddeb95fShamajima */ 66*fddeb95fShamajima 67*fddeb95fShamajima #define DVALID_REG_W 0x018 /* Data Valid Register */ 68*fddeb95fShamajima #define SODATV (1<<3) /* SODATREG Valid */ 69*fddeb95fShamajima #define SOMAV (1<<2) /* SDMADATREG Valid */ 70*fddeb95fShamajima #define MIDATV (1<<1) /* MIDATREG Valid */ 71*fddeb95fShamajima #define MDMAV (1) /* MDMADATREG Valid */ 72*fddeb95fShamajima 73*fddeb95fShamajima #define SEQ_REG_W 0x01a /* Sequencer Register */ 74*fddeb95fShamajima #define AIURST (1<<15) /* AIU Reset */ 75*fddeb95fShamajima #define AIUMEN (1<<4) /* Mic Enable */ 76*fddeb95fShamajima #define AIUSEN (1) /* Speaker Enable */ 77*fddeb95fShamajima 78*fddeb95fShamajima #define INT_REG_W 0x01c /* Interrupt Register */ 79*fddeb95fShamajima #define MENDINTR (1<<11) /* Mic End Interrupt */ 80*fddeb95fShamajima #define MINTR (1<<10) /* Mic Interrupt */ 81*fddeb95fShamajima #define MIDLEINTR (1<<9) /* Mic Idle Interrupt */ 82*fddeb95fShamajima #define MSTINTR (1<<8) /* Mic Set Interrupt */ 83*fddeb95fShamajima #define SENDINTR (1<<3) /* Speaker End Interrupt */ 84*fddeb95fShamajima #define SINTR (1<<2) /* Speaker Interrupt */ 85*fddeb95fShamajima #define SIDLEINTR (1<<1) /* Speaker Idle Interrupt */ 86