1*db2b0adeStakemura /* $NetBSD: dcureg.h,v 1.1.1.1 1999/09/16 12:23:32 takemura Exp $ */ 2*db2b0adeStakemura 3*db2b0adeStakemura /*- 4*db2b0adeStakemura * Copyright (c) 1999 SATO Kazumi. All rights reserved. 5*db2b0adeStakemura * Copyright (c) 1999 PocketBSD Project. All rights reserved. 6*db2b0adeStakemura * 7*db2b0adeStakemura * Redistribution and use in source and binary forms, with or without 8*db2b0adeStakemura * modification, are permitted provided that the following conditions 9*db2b0adeStakemura * are met: 10*db2b0adeStakemura * 1. Redistributions of source code must retain the above copyright 11*db2b0adeStakemura * notice, this list of conditions and the following disclaimer. 12*db2b0adeStakemura * 2. Redistributions in binary form must reproduce the above copyright 13*db2b0adeStakemura * notice, this list of conditions and the following disclaimer in the 14*db2b0adeStakemura * documentation and/or other materials provided with the distribution. 15*db2b0adeStakemura * 3. All advertising materials mentioning features or use of this software 16*db2b0adeStakemura * must display the following acknowledgement: 17*db2b0adeStakemura * This product includes software developed by the PocketBSD project 18*db2b0adeStakemura * and its contributors. 19*db2b0adeStakemura * 4. Neither the name of the project nor the names of its contributors 20*db2b0adeStakemura * may be used to endorse or promote products derived from this software 21*db2b0adeStakemura * without specific prior written permission. 22*db2b0adeStakemura * 23*db2b0adeStakemura * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24*db2b0adeStakemura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25*db2b0adeStakemura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26*db2b0adeStakemura * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27*db2b0adeStakemura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28*db2b0adeStakemura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29*db2b0adeStakemura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30*db2b0adeStakemura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31*db2b0adeStakemura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32*db2b0adeStakemura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33*db2b0adeStakemura * SUCH DAMAGE. 34*db2b0adeStakemura * 35*db2b0adeStakemura */ 36*db2b0adeStakemura 37*db2b0adeStakemura /* 38*db2b0adeStakemura * DCU (DMA Control UNIT) Registers. 39*db2b0adeStakemura * start 0x0B000040 40*db2b0adeStakemura */ 41*db2b0adeStakemura #define DMARST_REG_W 0x000 /* DMA Reset Register */ 42*db2b0adeStakemura #define DMARST (1) /* DMA reset */ 43*db2b0adeStakemura 44*db2b0adeStakemura #define DMAIDLE_REG_W 0x002 /* DMA Idle Register */ 45*db2b0adeStakemura #define DMAISTAT (1) /* DMA Idle Status */ 46*db2b0adeStakemura #define DMAIDLE (1) /* DMA Idle */ 47*db2b0adeStakemura #define DMABUSY (0) /* DMA Busy */ 48*db2b0adeStakemura 49*db2b0adeStakemura 50*db2b0adeStakemura #define DMASEN_REG_W 0x004 /* DMA Sequencer Enable Register */ 51*db2b0adeStakemura #define DMASENMASK (1) /* DMA Seq Enable */ 52*db2b0adeStakemura #define DMASEN (1) /* DMA Seq Enable */ 53*db2b0adeStakemura #define DMASDS (0) /* DMA Seq Disable */ 54*db2b0adeStakemura 55*db2b0adeStakemura 56*db2b0adeStakemura #define DMAMSK_REG_W 0x006 /* DMA Mask Register */ 57*db2b0adeStakemura #define DMAMSKAIN (1<<3) /* Audio IN DMA Enable */ 58*db2b0adeStakemura #define DMAMSKAOUT (1<<2) /* Audio OUT DMA Enable */ 59*db2b0adeStakemura #define DMAMSKFOUT (1) /* FIR DMA Enable */ 60*db2b0adeStakemura 61*db2b0adeStakemura 62*db2b0adeStakemura #define DMAREQ_REG_W 0x008 /* DMA Request Register */ 63*db2b0adeStakemura #define DMAREQAIN (1<<3) /* Audio IN Request pending */ 64*db2b0adeStakemura #define DMAREQAOUT (1<<2) /* Audio OUT Request pending */ 65*db2b0adeStakemura #define DMAREQFOUT (1) /* FIR Request pending */ 66*db2b0adeStakemura 67*db2b0adeStakemura 68*db2b0adeStakemura #define DMATD_REG_W 0x00A /* DMA Transfer Direction Register */ 69*db2b0adeStakemura #define DMATDMASK (1) /* DMA transfer direction (FIR) */ 70*db2b0adeStakemura #define DMATDIOMEM (1) /* I/O -> MEM */ 71*db2b0adeStakemura #define DMATDMEMIO (0) /* MEM -> I/O */ 72*db2b0adeStakemura 73*db2b0adeStakemura /* END dcureg.h */ 74