1*45dec0d1Stakemura /* $NetBSD: systeminfo.c,v 1.3 2000/01/16 03:07:33 takemura Exp $ */
29759fc21Stakemura
39759fc21Stakemura /*
49759fc21Stakemura * Copyright (c) 1999, by UCHIYAMA Yasushi
59759fc21Stakemura * All rights reserved.
69759fc21Stakemura *
79759fc21Stakemura * Redistribution and use in source and binary forms, with or without
89759fc21Stakemura * modification, are permitted provided that the following conditions
99759fc21Stakemura * are met:
109759fc21Stakemura * 1. Redistributions of source code must retain the above copyright
119759fc21Stakemura * notice, this list of conditions and the following disclaimer.
129759fc21Stakemura * 2. The name of the developer may NOT be used to endorse or promote products
139759fc21Stakemura * derived from this software without specific prior written permission.
149759fc21Stakemura *
159759fc21Stakemura * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
169759fc21Stakemura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
179759fc21Stakemura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
189759fc21Stakemura * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
199759fc21Stakemura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
209759fc21Stakemura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
219759fc21Stakemura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
229759fc21Stakemura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
239759fc21Stakemura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
249759fc21Stakemura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
259759fc21Stakemura * SUCH DAMAGE.
269759fc21Stakemura *
279759fc21Stakemura */
289759fc21Stakemura #include <pbsdboot.h>
29de467400Stakemura #include <machine/platid_mask.h>
30de467400Stakemura #if 0
319759fc21Stakemura #define PROCESSOR_LEVEL_R4000 4
329759fc21Stakemura #define PROCESSOR_LEVEL_R3000 3
339759fc21Stakemura #define PROCESSOR_REVMAJOR_VR41XX 0x0c
349759fc21Stakemura #define PROCESSOR_REVMAJOR_TX39XX 0x22
35de467400Stakemura #endif
369759fc21Stakemura
379759fc21Stakemura struct system_info system_info;
389759fc21Stakemura
399759fc21Stakemura static void dump_archinfo(SYSTEM_INFO*);
409759fc21Stakemura
419759fc21Stakemura int
set_system_info(platid_t * platid)42de467400Stakemura set_system_info(platid_t *platid)
439759fc21Stakemura {
449759fc21Stakemura SYSTEM_INFO info;
459759fc21Stakemura /*
469759fc21Stakemura * Set machine dependent information.
479759fc21Stakemura */
489759fc21Stakemura GetSystemInfo(&info);
49de467400Stakemura if (platid_match(platid, &platid_mask_CPU_MIPS)) {
50de467400Stakemura if (platid_match(platid, &platid_mask_CPU_MIPS_VR_41XX)) {
51de467400Stakemura vr41xx_init(&info);
52de467400Stakemura } else
53de467400Stakemura if (platid_match(platid, &platid_mask_CPU_MIPS_TX)) {
54de467400Stakemura tx39xx_init(&info);
55de467400Stakemura } else {
56de467400Stakemura dump_archinfo(&info);
57de467400Stakemura return 0;
58de467400Stakemura }
59de467400Stakemura } else {
60de467400Stakemura dump_archinfo(&info);
61de467400Stakemura return 0;
62de467400Stakemura }
63de467400Stakemura
64de467400Stakemura #if 0
659759fc21Stakemura switch (info.wProcessorArchitecture) {
669759fc21Stakemura default:
679759fc21Stakemura dump_archinfo(&info);
689759fc21Stakemura return 0;
699759fc21Stakemura break;
709759fc21Stakemura case PROCESSOR_ARCHITECTURE_MIPS:
719759fc21Stakemura switch (info.wProcessorLevel) {
729759fc21Stakemura default:
739759fc21Stakemura dump_archinfo(&info);
749759fc21Stakemura return 0;
759759fc21Stakemura break;
769759fc21Stakemura case PROCESSOR_LEVEL_R4000:
779759fc21Stakemura switch (info.wProcessorRevision >> 8) {
789759fc21Stakemura default:
799759fc21Stakemura dump_archinfo(&info);
809759fc21Stakemura return 0;
819759fc21Stakemura break;
829759fc21Stakemura case PROCESSOR_REVMAJOR_VR41XX:
839759fc21Stakemura vr41xx_init(&info);
849759fc21Stakemura break;
859759fc21Stakemura }
869759fc21Stakemura break;
879759fc21Stakemura case PROCESSOR_LEVEL_R3000:
889759fc21Stakemura switch (info.wProcessorRevision >> 8) {
899759fc21Stakemura default:
909759fc21Stakemura dump_archinfo(&info);
919759fc21Stakemura return 0;
929759fc21Stakemura break;
939759fc21Stakemura case PROCESSOR_REVMAJOR_TX39XX:
949759fc21Stakemura tx39xx_init(&info);
959759fc21Stakemura break;
969759fc21Stakemura }
979759fc21Stakemura break;
989759fc21Stakemura }
999759fc21Stakemura break;
1009759fc21Stakemura case PROCESSOR_ARCHITECTURE_SHx:
1019759fc21Stakemura dump_archinfo(&info);
1029759fc21Stakemura return 0;
1039759fc21Stakemura break;
1049759fc21Stakemura case PROCESSOR_ARCHITECTURE_ARM:
1059759fc21Stakemura dump_archinfo(&info);
1069759fc21Stakemura return 0;
1079759fc21Stakemura break;
1089759fc21Stakemura }
109de467400Stakemura #endif
1109759fc21Stakemura
1119759fc21Stakemura if (system_info.si_asmcodelen > (signed)system_info.si_pagesize) {
1129759fc21Stakemura msg_printf(MSG_ERROR, whoami,
1139759fc21Stakemura TEXT("asmcodelen=%d > pagesize=%d\n"),
1149759fc21Stakemura system_info.si_asmcodelen,
1159759fc21Stakemura system_info.si_pagesize);
1169759fc21Stakemura return 0;
1179759fc21Stakemura }
1189759fc21Stakemura
1199759fc21Stakemura return 1;
1209759fc21Stakemura }
1219759fc21Stakemura
1229759fc21Stakemura static void
dump_archinfo(SYSTEM_INFO * info)1239759fc21Stakemura dump_archinfo(SYSTEM_INFO *info)
1249759fc21Stakemura {
125de467400Stakemura msg_printf(MSG_ERROR, whoami, TEXT("Unsupported CPU\n"));
126de467400Stakemura #if 0
1279759fc21Stakemura msg_printf(MSG_ERROR, whoami,
1289759fc21Stakemura TEXT("Unknown machine ARCHITECTURE %#x, LEVEL %#x REVISION %#x.\n LCD(%dx%d)\n"),
1299759fc21Stakemura info->wProcessorArchitecture, info->wProcessorLevel,
1309759fc21Stakemura info->wProcessorRevision,
1319759fc21Stakemura GetSystemMetrics(SM_CXSCREEN),
1329759fc21Stakemura GetSystemMetrics(SM_CYSCREEN));
133de467400Stakemura #endif
1349759fc21Stakemura }
135