xref: /netbsd-src/sys/arch/hpcmips/dev/plumpowerreg.h (revision ce099b40997c43048fb78bd578195f81d2456523)
1*ce099b40Smartin /*	$NetBSD: plumpowerreg.h,v 1.4 2008/04/28 20:23:21 martin Exp $ */
29a758aabSuch 
3478ab76cSuch /*-
4478ab76cSuch  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
59a758aabSuch  * All rights reserved.
69a758aabSuch  *
7478ab76cSuch  * This code is derived from software contributed to The NetBSD Foundation
8478ab76cSuch  * by UCHIYAMA Yasushi.
9478ab76cSuch  *
109a758aabSuch  * Redistribution and use in source and binary forms, with or without
119a758aabSuch  * modification, are permitted provided that the following conditions
129a758aabSuch  * are met:
139a758aabSuch  * 1. Redistributions of source code must retain the above copyright
149a758aabSuch  *    notice, this list of conditions and the following disclaimer.
15478ab76cSuch  * 2. Redistributions in binary form must reproduce the above copyright
16478ab76cSuch  *    notice, this list of conditions and the following disclaimer in the
17478ab76cSuch  *    documentation and/or other materials provided with the distribution.
189a758aabSuch  *
19478ab76cSuch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20478ab76cSuch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21478ab76cSuch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22478ab76cSuch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23478ab76cSuch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24478ab76cSuch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25478ab76cSuch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26478ab76cSuch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27478ab76cSuch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28478ab76cSuch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29478ab76cSuch  * POSSIBILITY OF SUCH DAMAGE.
309a758aabSuch  */
319a758aabSuch 
329a758aabSuch /*
339a758aabSuch  * POWER CONTROLLER
349a758aabSuch  */
359a758aabSuch #define	PLUM_POWER_REGBASE		0x7000
369a758aabSuch #define	PLUM_POWER_REGSIZE		0x1000
379a758aabSuch 
389a758aabSuch /* power control register */
399a758aabSuch #define PLUM_POWER_PWRCONT_REG		0x000
409a758aabSuch 
419a758aabSuch #define PLUM_POWER_PWRCONT_USBEN	0x00000400
429a758aabSuch #define PLUM_POWER_PWRCONT_IO5OE	0x00000200
439a758aabSuch #define PLUM_POWER_PWRCONT_LCDOE	0x00000100
44478ab76cSuch /* EXTPW[0:2] Platform dependent control signal */
459a758aabSuch #define PLUM_POWER_PWRCONT_EXTPW2	0x00000040
469a758aabSuch #define PLUM_POWER_PWRCONT_EXTPW1	0x00000020
479a758aabSuch #define PLUM_POWER_PWRCONT_EXTPW0	0x00000010
489a758aabSuch #define PLUM_POWER_PWRCONT_IO5PWR	0x00000008
499a758aabSuch #define PLUM_POWER_PWRCONT_BKLIGHT	0x00000004
509a758aabSuch #define PLUM_POWER_PWRCONT_LCDPWR	0x00000002
519a758aabSuch #define PLUM_POWER_PWRCONT_LCDDSP	0x00000001
529a758aabSuch 
539a758aabSuch /* clock control register */
549a758aabSuch #define PLUM_POWER_CLKCONT_REG		0x004
559a758aabSuch 
569a758aabSuch #define	PLUM_POWER_CLKCONT_USBCLK2	0x00000020
579a758aabSuch #define	PLUM_POWER_CLKCONT_USBCLK1	0x00000010
589a758aabSuch #define	PLUM_POWER_CLKCONT_IO5CLK	0x00000008
599a758aabSuch #define	PLUM_POWER_CLKCONT_SMCLK	0x00000004
609a758aabSuch #define	PLUM_POWER_CLKCONT_PCCCLK2	0x00000002
619a758aabSuch #define	PLUM_POWER_CLKCONT_PCCCLK1	0x00000001
629a758aabSuch 
639a758aabSuch /* mask rom control register */
649a758aabSuch #define PLUM_POWER_MROMCNT_REG		0x008
659a758aabSuch 
669a758aabSuch #define PLUM_POWER_MROMCNT_MROMSL1	0x00000004
679a758aabSuch #define PLUM_POWER_MROMCNT_MROMSL0	0x00000002
689a758aabSuch #define PLUM_POWER_MROMCNT_MRMAEN	0x00000001
699a758aabSuch #define PLUM_POWER_MROMCNT_MROM_8MB	0x0
709a758aabSuch #define PLUM_POWER_MROMCNT_MROM_4MB	0x1
719a758aabSuch #define PLUM_POWER_MROMCNT_MROM_16MB	0x2
729a758aabSuch 
739a758aabSuch /* input signal enable register (MCS access) */
749a758aabSuch #define PLUM_POWER_INPENA_REG		0x00c
759a758aabSuch #define PLUM_POWER_INPENA		0x00000001
769a758aabSuch 
779a758aabSuch /* reset control register (I/O bus)*/
789a758aabSuch #define PLUM_POWER_RESETC_REG		0x010
79e96dc980Such /* Active High control */
809a758aabSuch #define PLUM_POWER_RESETC_IO5CL1	0x00000002
81e96dc980Such /* Active Low control */
829a758aabSuch #define PLUM_POWER_RESETC_IO5CL0	0x00000001
839a758aabSuch 
849a758aabSuch #define PLUM_POWER_TESTMD_REG		0x100
85