1*ce099b40Smartin /* -*-C++-*- $NetBSD: sh4.h,v 1.4 2008/04/28 20:23:20 martin Exp $ */ 2acb09f98Such 3acb09f98Such /*- 4acb09f98Such * Copyright (c) 2002 The NetBSD Foundation, Inc. 5acb09f98Such * All rights reserved. 6acb09f98Such * 7acb09f98Such * This code is derived from software contributed to The NetBSD Foundation 8acb09f98Such * by UCHIYAMA Yasushi. 9acb09f98Such * 10acb09f98Such * Redistribution and use in source and binary forms, with or without 11acb09f98Such * modification, are permitted provided that the following conditions 12acb09f98Such * are met: 13acb09f98Such * 1. Redistributions of source code must retain the above copyright 14acb09f98Such * notice, this list of conditions and the following disclaimer. 15acb09f98Such * 2. Redistributions in binary form must reproduce the above copyright 16acb09f98Such * notice, this list of conditions and the following disclaimer in the 17acb09f98Such * documentation and/or other materials provided with the distribution. 18acb09f98Such * 19acb09f98Such * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20acb09f98Such * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21acb09f98Such * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22acb09f98Such * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23acb09f98Such * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24acb09f98Such * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25acb09f98Such * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26acb09f98Such * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27acb09f98Such * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28acb09f98Such * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29acb09f98Such * POSSIBILITY OF SUCH DAMAGE. 30acb09f98Such */ 31acb09f98Such 32acb09f98Such #ifndef _HPCBOOT_SH_CPU_SH4_H_ 33acb09f98Such #define _HPCBOOT_SH_CPU_SH4_H_ 34acb09f98Such #include <sh3/cpu/sh.h> 35acb09f98Such 36acb09f98Such /* 37acb09f98Such * SH4 designed for Windows CE (SH7750) common defines. 38acb09f98Such */ 39acb09f98Such 40acb09f98Such #define SH4_TRA 0xff000020 41acb09f98Such #define SH4_EXPEVT 0xff000024 42acb09f98Such #define SH4_INTEVT 0xff000028 43acb09f98Such 44acb09f98Such #define SH4_ICR 0xffd00000 45acb09f98Such #define SH4_IPRA 0xffd00004 46acb09f98Such #define SH4_IPRB 0xffd00008 47acb09f98Such #define SH4_IPRC 0xffd0000c 48acb09f98Such #define SH4_IPRD 0xffd00010 49acb09f98Such 50acb09f98Such /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */ 51acb09f98Such #define SH4_PAGE_SIZE 0x1000 52acb09f98Such #define SH4_PAGE_MASK (~(SH4_PAGE_SIZE - 1)) 53acb09f98Such 54acb09f98Such /* 55acb09f98Such * Cache 56acb09f98Such */ 57acb09f98Such #define SH4_ICACHE_SIZE 8192 58acb09f98Such #define SH4_DCACHE_SIZE 16384 59acb09f98Such #define SH4_CACHE_LINESZ 32 60acb09f98Such 61acb09f98Such #define SH4_CCR 0xff00001c 62acb09f98Such #define SH4_CCR_IIX 0x00008000 63acb09f98Such #define SH4_CCR_ICI 0x00000800 64acb09f98Such #define SH4_CCR_ICE 0x00000100 65acb09f98Such #define SH4_CCR_OIX 0x00000080 66acb09f98Such #define SH4_CCR_ORA 0x00000020 67acb09f98Such #define SH4_CCR_OCI 0x00000008 68acb09f98Such #define SH4_CCR_CB 0x00000004 69acb09f98Such #define SH4_CCR_WT 0x00000002 70acb09f98Such #define SH4_CCR_OCE 0x00000001 71acb09f98Such 72acb09f98Such #define SH4_QACR0 0xff000038 73acb09f98Such #define SH4_QACR1 0xff00003c 74acb09f98Such #define SH4_QACR_AREA_SHIFT 2 75acb09f98Such #define SH4_QACR_AREA_MASK 0x0000001c 76acb09f98Such 77acb09f98Such /* I-cache address/data array */ 78acb09f98Such #define SH4REG_CCIA 0xf0000000 79acb09f98Such /* address specification */ 80acb09f98Such #define CCIA_A 0x00000008 /* associate bit */ 81acb09f98Such #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 82acb09f98Such #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 83acb09f98Such /* data specification */ 84acb09f98Such #define CCIA_V 0x00000001 85acb09f98Such #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 86acb09f98Such 87acb09f98Such #define SH4REG_CCID 0xf1000000 88acb09f98Such /* address specification */ 89acb09f98Such #define CCID_L_SHIFT 2 90acb09f98Such #define CCID_L_MASK 0x1c /* line-size is 32B */ 91acb09f98Such #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 92acb09f98Such 93acb09f98Such /* D-cache address/data array */ 94acb09f98Such #define SH4REG_CCDA 0xf4000000 95acb09f98Such /* address specification */ 96acb09f98Such #define CCDA_A 0x00000008 /* associate bit */ 97acb09f98Such #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 98acb09f98Such #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 99acb09f98Such /* data specification */ 100acb09f98Such #define CCDA_V 0x00000001 101acb09f98Such #define CCDA_U 0x00000002 102acb09f98Such #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 103acb09f98Such 104acb09f98Such #define SH4REG_CCDD 0xf5000000 105acb09f98Such 106acb09f98Such /* 107acb09f98Such * MMU 108acb09f98Such */ 109acb09f98Such #define SH4_PTEH 0xff000000 110acb09f98Such #define SH4_PTEH_ASID_MASK 0x0000000f 111acb09f98Such #define SH4_PTEL 0xff000004 112acb09f98Such #define SH4_PTEL_WT 0x00000001 113acb09f98Such #define SH4_PTEL_SH 0x00000002 114acb09f98Such #define SH4_PTEL_D 0x00000004 115acb09f98Such #define SH4_PTEL_C 0x00000008 116acb09f98Such #define SH4_PTEL_PR_SHIFT 5 117acb09f98Such #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 118acb09f98Such #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 119acb09f98Such #define SH4_PTEL_SZ_1K 0x00000000 120acb09f98Such #define SH4_PTEL_SZ_4K 0x00000010 121acb09f98Such #define SH4_PTEL_SZ_64K 0x00000080 122acb09f98Such #define SH4_PTEL_SZ_1M 0x00000090 123acb09f98Such #define SH4_PTEL_V 0x00000100 124acb09f98Such #define SH4_PTEA 0xff000034 125acb09f98Such #define SH4_PTEA_SA_MASK 0x00000007 126acb09f98Such #define SH4_PTEA_SA_TC 0x00000008 127acb09f98Such #define SH4_TTB 0xff000008 128acb09f98Such #define SH4_TTA 0xff00000c 129acb09f98Such #define SH4_MMUCR 0xff000010 130acb09f98Such #define SH4_MMUCR_AT 0x00000001 131acb09f98Such #define SH4_MMUCR_TI 0x00000004 132acb09f98Such #define SH4_MMUCR_SV 0x00000100 133acb09f98Such #define SH4_MMUCR_SQMD 0x00000200 134acb09f98Such #define SH4_MMUCR_URC_SHIFT 10 135acb09f98Such #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 136acb09f98Such #define SH4_MMUCR_URB_SHIFT 18 137acb09f98Such #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 138acb09f98Such #define SH4_MMUCR_LRUI_SHIFT 26 139acb09f98Such #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 140acb09f98Such /* 141acb09f98Such * memory-mapped TLB 142acb09f98Such * must be access from P2-area program. 143acb09f98Such * branch to the other area must be maed at least 8 instruction 144acb09f98Such * after access. 145acb09f98Such */ 146acb09f98Such /* ITLB */ 147acb09f98Such #define SH4_ITLB_AA 0xf2000000 148acb09f98Such /* address specification (common for address and data array(0,1)) */ 149acb09f98Such #define SH4_ITLB_E_SHIFT 8 150acb09f98Such #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 151acb09f98Such /* data specification */ 152acb09f98Such /* address-array */ 153acb09f98Such #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 154acb09f98Such #define SH4_ITLB_AA_V 0x00000100 155acb09f98Such #define SH4_ITLB_AA_VPN_SHIFT 10 156acb09f98Such #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 157acb09f98Such /* data-array 1 */ 158acb09f98Such #define SH4_ITLB_DA1 0xf3000000 159acb09f98Such #define SH4_ITLB_DA1_SH 0x00000002 160acb09f98Such #define SH4_ITLB_DA1_C 0x00000008 161acb09f98Such #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 162acb09f98Such #define SH4_ITLB_DA1_SZ_1K 0x00000000 163acb09f98Such #define SH4_ITLB_DA1_SZ_4K 0x00000010 164acb09f98Such #define SH4_ITLB_DA1_SZ_64K 0x00000080 165acb09f98Such #define SH4_ITLB_DA1_SZ_1M 0x00000090 166acb09f98Such #define SH4_ITLB_DA1_PR 0x00000040 167acb09f98Such #define SH4_ITLB_DA1_V 0x00000100 168acb09f98Such #define SH4_ITLB_DA1_PPN_SHIFT 11 169acb09f98Such #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 170acb09f98Such /* data-array 2 */ 171acb09f98Such #define SH4_ITLB_DA2 0xf3800000 172acb09f98Such #define SH4_ITLB_DA2_SA_MASK 0x00000003 173acb09f98Such #define SH4_ITLB_DA2_TC 0x00000004 174acb09f98Such 175acb09f98Such /* UTLB */ 176acb09f98Such #define SH4_UTLB_AA 0xf6000000 177acb09f98Such /* address specification (common for address and data array(0,1)) */ 178acb09f98Such #define SH4_UTLB_E_SHIFT 8 179acb09f98Such #define SH4_UTLB_E_MASK 0x00003f00 180acb09f98Such /* data specification */ 181acb09f98Such /* address-array */ 182acb09f98Such #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 183acb09f98Such #define SH4_UTLB_AA_D 0x00000200 184acb09f98Such #define SH4_UTLB_AA_V 0x00000100 185acb09f98Such #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 186acb09f98Such /* data-array 1 */ 187acb09f98Such #define SH4_UTLB_DA1 0xf7000000 188acb09f98Such #define SH4_UTLB_DA1_WT 0x00000001 189acb09f98Such #define SH4_UTLB_DA1_SH 0x00000002 190acb09f98Such #define SH4_UTLB_DA1_D 0x00000004 191acb09f98Such #define SH4_UTLB_DA1_C 0x00000008 192acb09f98Such #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 193acb09f98Such #define SH4_UTLB_DA1_SZ_1K 0x00000000 194acb09f98Such #define SH4_UTLB_DA1_SZ_4K 0x00000010 195acb09f98Such #define SH4_UTLB_DA1_SZ_64K 0x00000080 196acb09f98Such #define SH4_UTLB_DA1_SZ_1M 0x00000090 197acb09f98Such #define SH4_UTLB_DA1_PR_SHIFT 5 198acb09f98Such #define SH4_UTLB_DA1_PR_MASK 0x00000060 199acb09f98Such #define SH4_UTLB_DA1_V 0x00000100 200acb09f98Such #define SH4_UTLB_DA1_PPN_SHIFT 11 201acb09f98Such #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 202acb09f98Such /* data-array 2 */ 203acb09f98Such #define SH4_UTLB_DA2 0xf7800000 204acb09f98Such #define SH4_UTLB_DA2_SA_MASK 0x00000003 205acb09f98Such #define SH4_UTLB_DA2_TC 0x00000004 206acb09f98Such 207acb09f98Such #define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI) 208acb09f98Such 209acb09f98Such /* 210acb09f98Such * Product dependent headers 211acb09f98Such */ 212acb09f98Such #include <sh3/cpu/7750.h> 213acb09f98Such 214acb09f98Such #endif /* _HPCBOOT_SH_CPU_SH4_H_ */ 215