1*2388feefSnonaka /* $NetBSD: ap_ms104_sh4reg.h,v 1.2 2012/01/21 19:44:29 nonaka Exp $ */ 2238763f6Snonaka 3238763f6Snonaka /*- 4*2388feefSnonaka * Copyright (C) 2009 NONAKA Kimihiro <nonaka@netbsd.org> 5238763f6Snonaka * All rights reserved. 6238763f6Snonaka * 7238763f6Snonaka * Redistribution and use in source and binary forms, with or without 8238763f6Snonaka * modification, are permitted provided that the following conditions 9238763f6Snonaka * are met: 10238763f6Snonaka * 1. Redistributions of source code must retain the above copyright 11238763f6Snonaka * notice, this list of conditions and the following disclaimer. 12238763f6Snonaka * 2. Redistributions in binary form must reproduce the above copyright 13238763f6Snonaka * notice, this list of conditions and the following disclaimer in the 14238763f6Snonaka * documentation and/or other materials provided with the distribution. 15238763f6Snonaka * 16*2388feefSnonaka * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*2388feefSnonaka * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*2388feefSnonaka * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*2388feefSnonaka * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*2388feefSnonaka * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21*2388feefSnonaka * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22*2388feefSnonaka * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23*2388feefSnonaka * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24*2388feefSnonaka * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25*2388feefSnonaka * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26238763f6Snonaka */ 27238763f6Snonaka 28238763f6Snonaka #ifndef AP_MS104_SH4REG_H_ 29238763f6Snonaka #define AP_MS104_SH4REG_H_ 30238763f6Snonaka 31238763f6Snonaka #define EXTINTR_MASK1 0xa4000000 /* R/W: 8bit */ 32238763f6Snonaka #define EXTINTR_MASK2 0xa4100000 /* R/W: 8bit */ 33238763f6Snonaka #define EXTINTR_MASK3 0xa4200000 /* R/W: 8bit */ 34238763f6Snonaka #define EXTINTR_MASK4 0xa4300000 /* R/W: 8bit */ 35238763f6Snonaka #define EXTINTR_STAT1 0xa4400000 /* R: 8bit */ 36238763f6Snonaka #define EXTINTR_STAT2 0xa4500000 /* R: 8bit */ 37238763f6Snonaka #define EXTINTR_STAT3 0xa4600000 /* R: 8bit */ 38238763f6Snonaka #define EXTINTR_STAT4 0xa4700000 /* R: 8bit */ 39238763f6Snonaka #define CFBUS_CTRL 0xa4800000 /* W: 8bit */ 40238763f6Snonaka 41238763f6Snonaka /* EXTINTR_MASK1 */ 42238763f6Snonaka #define MASK1_INT14 (1U << 0) 43238763f6Snonaka #define MASK1_INT13 (1U << 1) 44238763f6Snonaka #define MASK1_INT12 (1U << 2) 45238763f6Snonaka #define MASK1_INT11 (1U << 3) 46238763f6Snonaka 47238763f6Snonaka /* EXTINTR_MASK2 */ 48238763f6Snonaka #define MASK2_INT10 (1U << 0) 49238763f6Snonaka #define MASK2_INT9 (1U << 1) 50238763f6Snonaka #define MASK2_INT8 (1U << 2) 51238763f6Snonaka #define MASK2_INT7 (1U << 3) 52238763f6Snonaka 53238763f6Snonaka /* EXTINTR_MASK3 */ 54238763f6Snonaka #define MASK3_INT6 (1U << 0) 55238763f6Snonaka #define MASK3_INT5 (1U << 1) 56238763f6Snonaka #define MASK3_INT4 (1U << 2) 57238763f6Snonaka #define MASK3_INT3 (1U << 3) 58238763f6Snonaka 59238763f6Snonaka /* EXTINTR_MASK4 */ 60238763f6Snonaka #define MASK4_INT2 (1U << 0) 61238763f6Snonaka #define MASK4_INT1 (1U << 1) 62238763f6Snonaka 63238763f6Snonaka /* EXTINTR_STAT1 */ 64238763f6Snonaka #define STAT1_INT14 (1U << 0) 65238763f6Snonaka #define STAT1_INT13 (1U << 1) 66238763f6Snonaka #define STAT1_INT12 (1U << 2) 67238763f6Snonaka #define STAT1_INT11 (1U << 3) 68238763f6Snonaka 69238763f6Snonaka /* EXTINTR_STAT2 */ 70238763f6Snonaka #define STAT2_INT10 (1U << 0) 71238763f6Snonaka #define STAT2_INT9 (1U << 1) 72238763f6Snonaka #define STAT2_INT8 (1U << 2) 73238763f6Snonaka #define STAT2_INT7 (1U << 3) 74238763f6Snonaka 75238763f6Snonaka /* EXTINTR_STAT3 */ 76238763f6Snonaka #define STAT3_INT6 (1U << 0) 77238763f6Snonaka #define STAT3_INT5 (1U << 1) 78238763f6Snonaka #define STAT3_INT4 (1U << 2) 79238763f6Snonaka #define STAT3_INT3 (1U << 3) 80238763f6Snonaka 81238763f6Snonaka /* EXTINTR_STAT4 */ 82238763f6Snonaka #define STAT4_INT2 (1U << 0) 83238763f6Snonaka #define STAT4_INT1 (1U << 1) 84238763f6Snonaka 85238763f6Snonaka /* CFBUS_CTRL */ 86238763f6Snonaka #define CFBUS_CTRL_WAIT (1U << 0) 87238763f6Snonaka #define CFBUS_CTRL_IOIS16 (1U << 1) 88238763f6Snonaka 89238763f6Snonaka /* external intr# */ 90238763f6Snonaka #define EXTINTR_INTR_SMC91C111 8 91238763f6Snonaka #define EXTINTR_INTR_CFIREQ 12 92238763f6Snonaka #define EXTINTR_INTR_RTC 14 93238763f6Snonaka 94238763f6Snonaka /* GPIO pin# */ 95238763f6Snonaka #define GPIO_PIN_CARD_CD 8 /* In */ 96238763f6Snonaka #define GPIO_PIN_CARD_PON 9 /* Out */ 97238763f6Snonaka #define GPIO_PIN_CARD_RESET 10 /* Out */ 98238763f6Snonaka #define GPIO_PIN_CARD_ENABLE 11 /* Out */ 99238763f6Snonaka #define GPIO_PIN_RTC_SIO 13 /* In/Out */ 100238763f6Snonaka #define GPIO_PIN_RTC_SCLK 14 /* Out */ 101238763f6Snonaka #define GPIO_PIN_RTC_CE 15 /* Out */ 102238763f6Snonaka 103238763f6Snonaka #endif /* AP_MS104_SH4REG_H_ */ 104