1*7433666eSthorpej /* $NetBSD: pci_machdep.c,v 1.7 2023/12/20 14:18:37 thorpej Exp $ */
2d974db0aSgarbled
3d974db0aSgarbled /*
4d974db0aSgarbled * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5d974db0aSgarbled * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6d974db0aSgarbled *
7d974db0aSgarbled * Redistribution and use in source and binary forms, with or without
8d974db0aSgarbled * modification, are permitted provided that the following conditions
9d974db0aSgarbled * are met:
10d974db0aSgarbled * 1. Redistributions of source code must retain the above copyright
11d974db0aSgarbled * notice, this list of conditions and the following disclaimer.
12d974db0aSgarbled * 2. Redistributions in binary form must reproduce the above copyright
13d974db0aSgarbled * notice, this list of conditions and the following disclaimer in the
14d974db0aSgarbled * documentation and/or other materials provided with the distribution.
15d974db0aSgarbled * 3. All advertising materials mentioning features or use of this software
16d974db0aSgarbled * must display the following acknowledgement:
17d974db0aSgarbled * This product includes software developed by Charles M. Hannum.
18d974db0aSgarbled * 4. The name of the author may not be used to endorse or promote products
19d974db0aSgarbled * derived from this software without specific prior written permission.
20d974db0aSgarbled *
21d974db0aSgarbled * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22d974db0aSgarbled * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23d974db0aSgarbled * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24d974db0aSgarbled * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25d974db0aSgarbled * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26d974db0aSgarbled * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27d974db0aSgarbled * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28d974db0aSgarbled * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29d974db0aSgarbled * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30d974db0aSgarbled * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31d974db0aSgarbled */
32d974db0aSgarbled
33d974db0aSgarbled /*
34d974db0aSgarbled * Machine-specific functions for PCI autoconfiguration.
35d974db0aSgarbled *
36d974db0aSgarbled * On PCs, there are two methods of generating PCI configuration cycles.
37d974db0aSgarbled * We try to detect the appropriate mechanism for this machine and set
38d974db0aSgarbled * up a few function pointers to access the correct method directly.
39d974db0aSgarbled *
40d974db0aSgarbled * The configuration method can be hard-coded in the config file by
41d974db0aSgarbled * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42d974db0aSgarbled * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43d974db0aSgarbled */
44d974db0aSgarbled
45d974db0aSgarbled #include <sys/cdefs.h>
46*7433666eSthorpej __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.7 2023/12/20 14:18:37 thorpej Exp $");
47d974db0aSgarbled
48d974db0aSgarbled #include <sys/param.h>
49dd2488a8Smatt #include <sys/bus.h>
50d974db0aSgarbled #include <sys/device.h>
51d974db0aSgarbled #include <sys/errno.h>
52d974db0aSgarbled #include <sys/extent.h>
53dd2488a8Smatt #include <sys/intr.h>
54d974db0aSgarbled #include <sys/queue.h>
55d974db0aSgarbled #include <sys/systm.h>
56d974db0aSgarbled #include <sys/time.h>
57d974db0aSgarbled
58d974db0aSgarbled #include <uvm/uvm.h>
59d974db0aSgarbled
60d974db0aSgarbled #define _POWERPC_BUS_DMA_PRIVATE
61d974db0aSgarbled
62d974db0aSgarbled #include <dev/ic/cpc700reg.h>
63dd2488a8Smatt
64d974db0aSgarbled #include <machine/pmppc.h>
65dd2488a8Smatt #include <machine/pio.h>
66d974db0aSgarbled
67d974db0aSgarbled #include <dev/pci/pcivar.h>
68d974db0aSgarbled #include <dev/pci/pcireg.h>
69d974db0aSgarbled #include <dev/pci/pcidevs.h>
70d974db0aSgarbled #include <dev/pci/pciconf.h>
71d974db0aSgarbled
72dd2488a8Smatt #include <evbppc/pmppc/dev/mainbus.h>
73d974db0aSgarbled
74d974db0aSgarbled /*
75d974db0aSgarbled * Address conversion as seen from a PCI master.
76d974db0aSgarbled * XXX Shouldn't use 0x80000000, the actual value
77d974db0aSgarbled * should come from the BAR.
78d974db0aSgarbled */
79d974db0aSgarbled #define PHYS_TO_PCI_MEM(x) ((x) + 0x80000000)
80d974db0aSgarbled #define PCI_MEM_TO_PHYS(x) ((x) - 0x80000000)
81d974db0aSgarbled
82d974db0aSgarbled static bus_addr_t phys_to_pci(bus_dma_tag_t, bus_addr_t);
83d974db0aSgarbled static bus_addr_t pci_to_phys(bus_dma_tag_t, bus_addr_t);
84d974db0aSgarbled
85d974db0aSgarbled extern struct powerpc_bus_dma_tag pci_bus_dma_tag;
86d974db0aSgarbled
87d974db0aSgarbled void
pmppc_pci_get_chipset_tag(pci_chipset_tag_t pc)88d974db0aSgarbled pmppc_pci_get_chipset_tag(pci_chipset_tag_t pc)
89d974db0aSgarbled {
90d974db0aSgarbled pc->pc_conf_v = (void *)pc;
91d974db0aSgarbled
92d974db0aSgarbled pc->pc_attach_hook = genppc_pci_indirect_attach_hook;
93d974db0aSgarbled pc->pc_bus_maxdevs = genppc_pci_bus_maxdevs;
94d974db0aSgarbled pc->pc_make_tag = genppc_pci_indirect_make_tag;
95d974db0aSgarbled pc->pc_conf_read = genppc_pci_indirect_conf_read;
96d974db0aSgarbled pc->pc_conf_write = genppc_pci_indirect_conf_write;
97d974db0aSgarbled
98d974db0aSgarbled pc->pc_intr_v = (void *)pc;
99d974db0aSgarbled
100d974db0aSgarbled pc->pc_intr_map = pmppc_pci_intr_map;
101d974db0aSgarbled pc->pc_intr_string = genppc_pci_intr_string;
102d974db0aSgarbled pc->pc_intr_evcnt = genppc_pci_intr_evcnt;
103d974db0aSgarbled pc->pc_intr_establish = genppc_pci_intr_establish;
104d974db0aSgarbled pc->pc_intr_disestablish = genppc_pci_intr_disestablish;
105dd2488a8Smatt pc->pc_intr_setattr = genppc_pci_intr_setattr;
106e4a54b41Snonaka pc->pc_intr_type = genppc_pci_intr_type;
107e4a54b41Snonaka pc->pc_intr_alloc = genppc_pci_intr_alloc;
108e4a54b41Snonaka pc->pc_intr_release = genppc_pci_intr_release;
109e4a54b41Snonaka pc->pc_intx_alloc = genppc_pci_intx_alloc;
110e4a54b41Snonaka
111e4a54b41Snonaka pc->pc_msi_v = (void *)pc;
112e4a54b41Snonaka genppc_pci_chipset_msi_init(pc);
113e4a54b41Snonaka
114e4a54b41Snonaka pc->pc_msix_v = (void *)pc;
115e4a54b41Snonaka genppc_pci_chipset_msix_init(pc);
116d974db0aSgarbled
117d974db0aSgarbled pc->pc_conf_interrupt = pmppc_pci_conf_interrupt;
118d974db0aSgarbled pc->pc_decompose_tag = genppc_pci_indirect_decompose_tag;
119d974db0aSgarbled pc->pc_conf_hook = genppc_pci_conf_hook;
120d974db0aSgarbled
1214a40b014Smatt pc->pc_addr = mapiodev(CPC_PCICFGADR, 4, false);
1224a40b014Smatt pc->pc_data = mapiodev(CPC_PCICFGDATA, 4, false);
123d974db0aSgarbled pc->pc_bus = 0;
124d974db0aSgarbled pc->pc_node = 0;
125d974db0aSgarbled pc->pc_memt = 0;
126d974db0aSgarbled pc->pc_iot = 0;
127d974db0aSgarbled
128d974db0aSgarbled /* the following two lines are required because unlike other ports,
129d974db0aSgarbled * we cannot just add PHYS_TO_BUS_MEM/BUS_MEM_TO_PHYS defines to
130d974db0aSgarbled * bus.h, because it would impact other evbppc ports.
131d974db0aSgarbled */
132d974db0aSgarbled pci_bus_dma_tag._dma_phys_to_bus_mem = phys_to_pci;
133d974db0aSgarbled pci_bus_dma_tag._dma_bus_mem_to_phys = pci_to_phys;
134d974db0aSgarbled }
135d974db0aSgarbled
136d974db0aSgarbled
137d974db0aSgarbled static bus_addr_t
phys_to_pci(bus_dma_tag_t t,bus_addr_t a)138d974db0aSgarbled phys_to_pci(bus_dma_tag_t t, bus_addr_t a)
139d974db0aSgarbled {
140d974db0aSgarbled return PHYS_TO_PCI_MEM(a);
141d974db0aSgarbled }
142d974db0aSgarbled
pci_to_phys(bus_dma_tag_t t,bus_addr_t a)143d974db0aSgarbled static bus_addr_t pci_to_phys(bus_dma_tag_t t, bus_addr_t a)
144d974db0aSgarbled {
145d974db0aSgarbled return PCI_MEM_TO_PHYS(a);
146d974db0aSgarbled }
147d974db0aSgarbled
148d974db0aSgarbled int
pmppc_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)149d3e53912Sdyoung pmppc_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
150d974db0aSgarbled {
151d974db0aSgarbled int pin = pa->pa_intrpin;
152d974db0aSgarbled int line = pa->pa_intrline;
153d974db0aSgarbled
154d974db0aSgarbled if (pin == 0) {
155d974db0aSgarbled /* No IRQ used. */
156d974db0aSgarbled goto bad;
157d974db0aSgarbled }
158d974db0aSgarbled
159d974db0aSgarbled if (pin > 4) {
160d974db0aSgarbled printf("pci_intr_map: bad interrupt pin %d\n", pin);
161d974db0aSgarbled goto bad;
162d974db0aSgarbled }
163d974db0aSgarbled
164d974db0aSgarbled if (line == 255) {
165d974db0aSgarbled printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
166d974db0aSgarbled goto bad;
167d974db0aSgarbled }
168d974db0aSgarbled /*printf("pci_intr_map pin=%d line=%d\n", pin, line);*/
169d974db0aSgarbled
170d974db0aSgarbled switch (line & 3) { /* XXX what should this be? */
171d974db0aSgarbled case 0: *ihp = PMPPC_I_BPMC_INTA; break;
172d974db0aSgarbled case 1: *ihp = PMPPC_I_BPMC_INTB; break;
173d974db0aSgarbled case 2: *ihp = PMPPC_I_BPMC_INTC; break;
174d974db0aSgarbled case 3: *ihp = PMPPC_I_BPMC_INTD; break;
175d974db0aSgarbled }
176d974db0aSgarbled return 0;
177d974db0aSgarbled
178d974db0aSgarbled bad:
179d974db0aSgarbled *ihp = -1;
180d974db0aSgarbled return 1;
181d974db0aSgarbled }
182d974db0aSgarbled
183d974db0aSgarbled void
pmppc_pci_conf_interrupt(void * v,int bus,int dev,int pin,int swiz,int * iline)184dd2488a8Smatt pmppc_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
185dd2488a8Smatt int *iline)
186d974db0aSgarbled {
187d974db0aSgarbled int line;
188d974db0aSgarbled
189d974db0aSgarbled line = (swiz + dev) & 3;
190d974db0aSgarbled /* XXX UGLY UGLY, figure out the real interrupt mapping */
191d974db0aSgarbled if (bus==3&&dev==2&&pin==1&&swiz==3) line=2;
192d974db0aSgarbled /*
193d974db0aSgarbled printf("pci_conf_interrupt: bus=%d dev=%d pin=%d swiz=%d => line=%d\n",
194d974db0aSgarbled bus, dev, pin, swiz, line);
195d974db0aSgarbled */
196d974db0aSgarbled *iline = line;
197d974db0aSgarbled }
198