1*70e231c9Smrg /* $NetBSD: swarm.h,v 1.1.1.1 2017/07/24 09:21:50 mrg Exp $ */ 2*70e231c9Smrg 3*70e231c9Smrg /* 4*70e231c9Smrg * I/O Address assignments for the CSWARM board 5*70e231c9Smrg * 6*70e231c9Smrg * Summary of address map: 7*70e231c9Smrg * 8*70e231c9Smrg * Address Size CSel Description 9*70e231c9Smrg * --------------- ---- ------ -------------------------------- 10*70e231c9Smrg * 0x1FC00000 2MB CS0 Boot ROM 11*70e231c9Smrg * 0x1F800000 2MB CS1 Alternate boot ROM 12*70e231c9Smrg * CS2 Unused 13*70e231c9Smrg * 0x100A0000 64KB CS3 LED display 14*70e231c9Smrg * 0x100B0000 64KB CS4 IDE Disk 15*70e231c9Smrg * CS5 Unused 16*70e231c9Smrg * 0x11000000 64MB CS6 PCMCIA 17*70e231c9Smrg * CS7 Unused 18*70e231c9Smrg * 19*70e231c9Smrg * GPIO assignments 20*70e231c9Smrg * 21*70e231c9Smrg * GPIO# Direction Description 22*70e231c9Smrg * ------- --------- ------------------------------------------ 23*70e231c9Smrg * GPIO0 Output Debug LED 24*70e231c9Smrg * GPIO1 Output Sturgeon NMI 25*70e231c9Smrg * GPIO2 Input PHY Interrupt (interrupt) 26*70e231c9Smrg * GPIO3 Input Nonmaskable Interrupt (interrupt) 27*70e231c9Smrg * GPIO4 Input IDE Disk Interrupt (interrupt) 28*70e231c9Smrg * GPIO5 Input Temperature Sensor Alert (interrupt) 29*70e231c9Smrg * GPIO6 N/A PCMCIA interface 30*70e231c9Smrg * GPIO7 N/A PCMCIA interface 31*70e231c9Smrg * GPIO8 N/A PCMCIA interface 32*70e231c9Smrg * GPIO9 N/A PCMCIA interface 33*70e231c9Smrg * GPIO10 N/A PCMCIA interface 34*70e231c9Smrg * GPIO11 N/A PCMCIA interface 35*70e231c9Smrg * GPIO12 N/A PCMCIA interface 36*70e231c9Smrg * GPIO13 N/A PCMCIA interface 37*70e231c9Smrg * GPIO14 N/A PCMCIA interface 38*70e231c9Smrg * GPIO15 N/A PCMCIA interface 39*70e231c9Smrg */ 40*70e231c9Smrg 41*70e231c9Smrg 42*70e231c9Smrg /* GPIO pins */ 43*70e231c9Smrg #define GPIO_DEBUG_LED 0 44*70e231c9Smrg #define GPIO_STURGEON_NMI 1 45*70e231c9Smrg #define GPIO_PHY_INTERRUPT 2 46*70e231c9Smrg #define GPIO_NONMASKABLE_INT 3 47*70e231c9Smrg #define GPIO_IDE_INTERRUPT 4 48*70e231c9Smrg #define GPIO_TEMP_SENSOR_INT 5 49*70e231c9Smrg 50*70e231c9Smrg /* device addresses */ 51*70e231c9Smrg #define SWARM_LEDS_PHYS 0x100a0000 52*70e231c9Smrg #define SWARM_IDE_PHYS 0x100b0000 53*70e231c9Smrg #define SWARM_PCMCIA_PHYS 0x11000000 54*70e231c9Smrg 55*70e231c9Smrg /* SMBus devices */ 56*70e231c9Smrg #define TEMPSENSOR_SMBUS_CHAN 0 57*70e231c9Smrg #define TEMPSENSOR_SMBUS_DEV 0x2A 58*70e231c9Smrg 59*70e231c9Smrg #define DRAM_SMBUS_CHAN 0 60*70e231c9Smrg #define DRAM_SMBUS_DEV 0x54 61*70e231c9Smrg 62*70e231c9Smrg #define BIGEEPROM_SMBUS_CHAN 0 63*70e231c9Smrg #define BIGEEPROM_SMBUS_DEV 0x50 64*70e231c9Smrg 65*70e231c9Smrg #define BIGEEPROM_SMBUS_CHAN_1 1 /* rev 2.0 swarm only */ 66*70e231c9Smrg #define BIGEEPROM_SMBUS_DEV_1 0x51 67*70e231c9Smrg 68*70e231c9Smrg #define CFG_DRAM_SMBUS_CHAN 0 69*70e231c9Smrg #define CFG_DRAM_SMBUS_BASE 0x54 /* starting SMBus device base */ 70*70e231c9Smrg 71*70e231c9Smrg #define X1241_SMBUS_CHAN 1 /* rev 1.0 swarm only, fixed slave address */ 72*70e231c9Smrg 73*70e231c9Smrg #define M41T81_SMBUS_CHAN 1 /* rev 2.0 swarm only (or PCF8563), fixed slave address */ 74*70e231c9Smrg 75*70e231c9Smrg #define PCF8563_SMBUS_CHAN 1 /* rev 2.0 swarm only (or M41T81) */ 76*70e231c9Smrg #define PCF8563_SMBUS_DEV 0x50 77*70e231c9Smrg 78*70e231c9Smrg #define MAX1617A_SMBUS_CHAN 0 /* or MAX6654 on newer board, reg compatible */ 79*70e231c9Smrg #define MAX1617A_SMBUS_DEV 0x2a 80