1*c62a0ac4Smatt /* $Id: mpcsa_io.h,v 1.2 2008/07/03 01:15:39 matt Exp $ */ 2*c62a0ac4Smatt 3*c62a0ac4Smatt #ifndef _mpcsa_io_h_ 4*c62a0ac4Smatt #define _mpcsa_io_h_ 1 5*c62a0ac4Smatt 6*c62a0ac4Smatt /* port A pins (bit numbers): */ 7*c62a0ac4Smatt #define PA_RTSD 29U 8*c62a0ac4Smatt #define PA_CTSD 28U 9*c62a0ac4Smatt #define PA_GSMOFF 27U 10*c62a0ac4Smatt #define PA_SCL 26U 11*c62a0ac4Smatt #define PA_SDA 25U 12*c62a0ac4Smatt #define PA_GSMON 24U 13*c62a0ac4Smatt #define PA_EXP1 9U 14*c62a0ac4Smatt #define PA_EXP0 8U 15*c62a0ac4Smatt #define PA_TXD4 5U 16*c62a0ac4Smatt #define PA_SPICS1 4U 17*c62a0ac4Smatt #define PA_SPICS0 3U 18*c62a0ac4Smatt #define PA_SPCK 2U 19*c62a0ac4Smatt #define PA_MOSI 1U 20*c62a0ac4Smatt #define PA_MISO 0U 21*c62a0ac4Smatt 22*c62a0ac4Smatt /* port B pins: */ 23*c62a0ac4Smatt #define PB_CTS4 29U 24*c62a0ac4Smatt #define PB_CTS3 28U 25*c62a0ac4Smatt #define PB_CTS2 27U 26*c62a0ac4Smatt #define PB_CTS1 26U 27*c62a0ac4Smatt #define PB_RTS4 25U 28*c62a0ac4Smatt #define PB_RTS3 24U 29*c62a0ac4Smatt #define PB_RTS2 23U 30*c62a0ac4Smatt #define PB_RTS1 22U 31*c62a0ac4Smatt #define PB_DIN4 14U 32*c62a0ac4Smatt #define PB_DIN3 13U 33*c62a0ac4Smatt #define PB_DIN2 12U 34*c62a0ac4Smatt #define PB_DIN1 11U 35*c62a0ac4Smatt #define PB_RXD6 10U 36*c62a0ac4Smatt #define PB_TXE6 9U 37*c62a0ac4Smatt #define PB_TXE5 7U 38*c62a0ac4Smatt #define PB_RXD5 6U 39*c62a0ac4Smatt #define PB_S_RF 5U 40*c62a0ac4Smatt #define PB_S_RK 4U 41*c62a0ac4Smatt #define PB_S_RD 3U 42*c62a0ac4Smatt #define PB_S_TD 2U 43*c62a0ac4Smatt #define PB_S_TK 1U 44*c62a0ac4Smatt #define PB_S_TF 0U 45*c62a0ac4Smatt 46*c62a0ac4Smatt /* port C pins: */ 47*c62a0ac4Smatt #define PC_CFRESET 5U 48*c62a0ac4Smatt #define PC_CFCD 4U 49*c62a0ac4Smatt #define PC_CFIRQ 3U 50*c62a0ac4Smatt #define PC_DSRD 1U 51*c62a0ac4Smatt #define PC_DTRD 0U 52*c62a0ac4Smatt 53*c62a0ac4Smatt /* port D pins: */ 54*c62a0ac4Smatt #define PD_DSR4 27U 55*c62a0ac4Smatt #define PD_DSR3 26U 56*c62a0ac4Smatt #define PD_DSR2 25U 57*c62a0ac4Smatt #define PD_DSR1 24U 58*c62a0ac4Smatt #define PD_DTR4 23U 59*c62a0ac4Smatt #define PD_DTR3 22U 60*c62a0ac4Smatt #define PD_DTR2 21U 61*c62a0ac4Smatt #define PD_DTR1 20U 62*c62a0ac4Smatt #define PD_SPICS2 19U 63*c62a0ac4Smatt #define PD_DCD4 18U 64*c62a0ac4Smatt #define PD_K702 17U 65*c62a0ac4Smatt #define PD_K701 16U 66*c62a0ac4Smatt #define PD_SW1 15U 67*c62a0ac4Smatt #define PD_SW2 14U 68*c62a0ac4Smatt #define PD_SW3 13U 69*c62a0ac4Smatt #define PD_SW4 12U 70*c62a0ac4Smatt #define PD_RESET_OUT 6U 71*c62a0ac4Smatt 72*c62a0ac4Smatt /* Leds behind SPI: */ 73*c62a0ac4Smatt #define PSPI_ELED43 11U 74*c62a0ac4Smatt #define PSPI_ELED33 10U 75*c62a0ac4Smatt #define PSPI_ELED23 9U 76*c62a0ac4Smatt #define PSPI_ELED13 8U 77*c62a0ac4Smatt #define PSPI_RLED1 7U 78*c62a0ac4Smatt #define PSPI_GLED2 6U 79*c62a0ac4Smatt #define PSPI_GLED1 5U 80*c62a0ac4Smatt #define PSPI_SLED5 4U 81*c62a0ac4Smatt #define PSPI_SLED4 3U 82*c62a0ac4Smatt #define PSPI_SLED3 2U 83*c62a0ac4Smatt #define PSPI_SLED2 1U 84*c62a0ac4Smatt #define PSPI_SLED1 0U 85*c62a0ac4Smatt 86*c62a0ac4Smatt 87*c62a0ac4Smatt /* led numbers: */ 88*c62a0ac4Smatt enum { 89*c62a0ac4Smatt LED_SER1 = 1, 90*c62a0ac4Smatt LED_SER2, 91*c62a0ac4Smatt LED_SER3, 92*c62a0ac4Smatt LED_SER4, 93*c62a0ac4Smatt LED_SER5, 94*c62a0ac4Smatt LED_SER_MAX = LED_SER5, 95*c62a0ac4Smatt LED_GSM, 96*c62a0ac4Smatt LED_GSM_LINK, 97*c62a0ac4Smatt LED_HB, 98*c62a0ac4Smatt LED_ETH1, 99*c62a0ac4Smatt LED_ETH2, 100*c62a0ac4Smatt LED_ETH3, 101*c62a0ac4Smatt LED_ETH4, 102*c62a0ac4Smatt LED_MAX 103*c62a0ac4Smatt }; 104*c62a0ac4Smatt 105*c62a0ac4Smatt #define NUM_ETH_PORTS 4 // amount of ethernet ports 106*c62a0ac4Smatt 107*c62a0ac4Smatt #endif /* _mpcsa_io_h_ */ 108