1*02cb47caStsutsui /* $NetBSD: z8530var.h,v 1.4 2008/03/29 19:15:34 tsutsui Exp $ */ 2e047259aSdrochner 3e047259aSdrochner #include <dev/ic/z8530sc.h> 4e047259aSdrochner 5e047259aSdrochner struct zsc_softc { 6*02cb47caStsutsui device_t zsc_dev; /* required first: base device */ 7e047259aSdrochner struct zs_chanstate *zsc_cs[2]; /* channel A and B soft state */ 8e047259aSdrochner /* Machine-dependent part follows... */ 90092fa7cStsutsui void *zsc_softintr_cookie; 10e047259aSdrochner }; 11e047259aSdrochner 12*02cb47caStsutsui uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg); 13*02cb47caStsutsui uint8_t zs_read_csr(struct zs_chanstate *cs); 14*02cb47caStsutsui uint8_t zs_read_data(struct zs_chanstate *cs); 15e047259aSdrochner 16*02cb47caStsutsui void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val); 17*02cb47caStsutsui void zs_write_csr(struct zs_chanstate *cs, uint8_t val); 18*02cb47caStsutsui void zs_write_data(struct zs_chanstate *cs, uint8_t val); 19e047259aSdrochner 20e047259aSdrochner /* Interrupt priority for the SCC chip; needs to match ZSHARD_PRI. */ 21e047259aSdrochner #define splzs() spl4() 22d3793569Sad #define IPL_ZS IPL_HIGH 23d3793569Sad 24