1*bc1ed5acSkiyohara /* $NetBSD: bebox.h,v 1.2 2012/10/20 12:37:49 kiyohara Exp $ */ 2f3244f97Skiyohara /* 3f3244f97Skiyohara * Copyright (c) 2011 KIYOHARA Takashi 4f3244f97Skiyohara * All rights reserved. 5f3244f97Skiyohara * 6f3244f97Skiyohara * Redistribution and use in source and binary forms, with or without 7f3244f97Skiyohara * modification, are permitted provided that the following conditions 8f3244f97Skiyohara * are met: 9f3244f97Skiyohara * 1. Redistributions of source code must retain the above copyright 10f3244f97Skiyohara * notice, this list of conditions and the following disclaimer. 11f3244f97Skiyohara * 2. Redistributions in binary form must reproduce the above copyright 12f3244f97Skiyohara * notice, this list of conditions and the following disclaimer in the 13f3244f97Skiyohara * documentation and/or other materials provided with the distribution. 14f3244f97Skiyohara * 15f3244f97Skiyohara * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16f3244f97Skiyohara * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17f3244f97Skiyohara * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18f3244f97Skiyohara * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19f3244f97Skiyohara * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20f3244f97Skiyohara * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21f3244f97Skiyohara * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22f3244f97Skiyohara * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23f3244f97Skiyohara * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24f3244f97Skiyohara * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25f3244f97Skiyohara * POSSIBILITY OF SUCH DAMAGE. 26f3244f97Skiyohara */ 27f3244f97Skiyohara 28f3244f97Skiyohara #ifndef _BEBOX_H 29f3244f97Skiyohara #define _BEBOX_H 30f3244f97Skiyohara 31f3244f97Skiyohara /* 32f3244f97Skiyohara * BeBox mainboard's Register 33f3244f97Skiyohara */ 34f3244f97Skiyohara #define BEBOX_REG 0x7ffff000 35f3244f97Skiyohara 36f3244f97Skiyohara #define BEBOX_SET_MASK 0x80000000 37f3244f97Skiyohara #define BEBOX_CLEAR_MASK 0x00000000 38f3244f97Skiyohara 39*bc1ed5acSkiyohara #define READ_BEBOX_REG(reg) *(volatile uint32_t *)(BEBOX_REG + (reg)) 40f3244f97Skiyohara #define SET_BEBOX_REG(reg, v) \ 41*bc1ed5acSkiyohara *(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK) 42f3244f97Skiyohara #define CLEAR_BEBOX_REG(reg, v) \ 43*bc1ed5acSkiyohara *(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK) 44f3244f97Skiyohara 45f3244f97Skiyohara #define CPU0_INT_MASK 0x0f0 /* Interrupt Mask for CPU0 */ 46f3244f97Skiyohara #define CPU1_INT_MASK 0x1f0 /* Interrupt Mask for CPU1 */ 47f3244f97Skiyohara #define INT_SOURCE 0x2f0 /* Interrupt Source */ 48f3244f97Skiyohara #define CPU_CONTROL 0x3f0 /* Inter-CPU Interrupt */ 49f3244f97Skiyohara #define CPU_RESET 0x4f0 /* Reset Control */ 50f3244f97Skiyohara #define INTR_VECTOR_REG 0xff0 51f3244f97Skiyohara 52*bc1ed5acSkiyohara #define BEBOX_INTR_MASK 0x0ffffffc 53*bc1ed5acSkiyohara 54f3244f97Skiyohara /* Control */ 55f3244f97Skiyohara #define CPU0_SMI (1 << 30) /* SMI to CPU0 */ 56f3244f97Skiyohara #define CPU1_SMI (1 << 29) /* SMI to CPU1 */ 57f3244f97Skiyohara #define CPU1_INT (1 << 28) /* Interrupt to CPU1 (rev.1 only) */ 58f3244f97Skiyohara #define CPU0_TLBISYNC (1 << 27) /* tlbsync to CPU0 */ 59f3244f97Skiyohara #define CPU1_TLBISYNC (1 << 26) /* tlbsync to CPU1 */ 60f3244f97Skiyohara #define WHO_AM_I (1 << 25) 61f3244f97Skiyohara 62f3244f97Skiyohara #define TLBISYNC_FROM(n) (1 << (CPU1_TLBISYNC + (n))) 63f3244f97Skiyohara 64f3244f97Skiyohara /* Reset */ 65f3244f97Skiyohara #define CPU1_SRESET (1 << 30) /* Software Reset to CPU1 */ 66f3244f97Skiyohara #define CPU1_HRESET (1 << 29) /* Hardware Reset to CPU1 */ 67f3244f97Skiyohara 68f3244f97Skiyohara #endif /* _BEBOX_H */ 69