xref: /netbsd-src/sys/arch/arm/xilinx/files.zynq (revision 5754a6ff213a9a342c74094c40f8c974d80dffb3)
1*5754a6ffSjmcneill#	$NetBSD: files.zynq,v 1.5 2022/11/11 20:31:30 jmcneill Exp $
2c8c5b6beSskrll#
3c8c5b6beSskrll# Configuration info for Xilinx Zynq-7000 SoC
4c8c5b6beSskrll#
5c8c5b6beSskrll#
6c8c5b6beSskrll
7c8c5b6beSskrllfile	arch/arm/xilinx/zynq_platform.c		soc_zynq
8c8c5b6beSskrll
9c8c5b6beSskrll# SOC parameters
10c8c5b6beSskrlldefflag	opt_soc.h				SOC_ZYNQ
11c8c5b6beSskrlldefflag	opt_soc.h				SOC_ZYNQ7000: SOC_ZYNQ
12c8c5b6beSskrll
13479d0371Sjmcneill# PS clock subsystem
14479d0371Sjmcneilldevice	zynqclk
15479d0371Sjmcneillattach	zynqclk at fdt with zynq7000_clkc
16479d0371Sjmcneillfile	arch/arm/xilinx/zynq7000_clkc.c		zynq7000_clkc
17479d0371Sjmcneill
18c5633092Sjmcneill# GPIO
19c5633092Sjmcneilldevice	zynqgpio: gpiobus
20c5633092Sjmcneillattach	zynqgpio at fdt
21c5633092Sjmcneillfile	arch/arm/xilinx/zynq_gpio.c		zynqgpio
22c5633092Sjmcneill
23c8c5b6beSskrll# UART
24c8c5b6beSskrlldevice	zynquart
25c8c5b6beSskrllattach	zynquart at fdt
26c8c5b6beSskrllfile	arch/arm/xilinx/zynq_uart.c		zynquart needs-flag
27c8c5b6beSskrllfile	arch/arm/xilinx/zynq7000_uart.c		zynquart
28c8c5b6beSskrlldefflag	opt_zynquart.h				ZYNQUARTCONSOLE
29c8c5b6beSskrll
30c8c5b6beSskrll# Gigabit Ethernet Controller
31c8c5b6beSskrlldevice	cemac: ether, ifnet, arp, mii, bus_dma_generic
32c8c5b6beSskrllattach	cemac at fdt
33c8c5b6beSskrllfile	dev/cadence/if_cemac.c			cemac
34c8c5b6beSskrllfile	arch/arm/xilinx/zynq_cemac.c		cemac
35c8c5b6beSskrll
36c8c5b6beSskrll# USB controller
37c8c5b6beSskrllattach	ehci at fdt with zynqusb
38c8c5b6beSskrllfile	arch/arm/xilinx/zynq_usb.c		zynqusb
39c8c5b6beSskrllfile	arch/arm/xilinx/zynq7000_usb.c		zynqusb
40*5754a6ffSjmcneill
41*5754a6ffSjmcneill# Xilinx 7 series ADC
42*5754a6ffSjmcneilldevice	zynqxadc: sysmon_envsys
43*5754a6ffSjmcneillattach	zynqxadc at fdt
44*5754a6ffSjmcneillfile	arch/arm/xilinx/zynq_xadc.c		zynqxadc
45