xref: /netbsd-src/sys/arch/arm/sunxi/sunxi_lradc.h (revision 6bdb7968c2a5f6966f7e79d3f23c23c92bb797a1)
1*6bdb7968Sbouyer /* $NetBSD: sunxi_lradc.h,v 1.1 2018/03/07 20:55:31 bouyer Exp $ */
2*6bdb7968Sbouyer 
3*6bdb7968Sbouyer /*-
4*6bdb7968Sbouyer  * Copyright (c) 2016 Manuel Bouyer
5*6bdb7968Sbouyer  * All rights reserved.
6*6bdb7968Sbouyer  *
7*6bdb7968Sbouyer  * Redistribution and use in source and binary forms, with or without
8*6bdb7968Sbouyer  * modification, are permitted provided that the following conditions
9*6bdb7968Sbouyer  * are met:
10*6bdb7968Sbouyer  * 1. Redistributions of source code must retain the above copyright
11*6bdb7968Sbouyer  *    notice, this list of conditions and the following disclaimer.
12*6bdb7968Sbouyer  * 2. Redistributions in binary form must reproduce the above copyright
13*6bdb7968Sbouyer  *    notice, this list of conditions and the following disclaimer in the
14*6bdb7968Sbouyer  *    documentation and/or other materials provided with the distribution.
15*6bdb7968Sbouyer  *
16*6bdb7968Sbouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17*6bdb7968Sbouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18*6bdb7968Sbouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19*6bdb7968Sbouyer  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20*6bdb7968Sbouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21*6bdb7968Sbouyer  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22*6bdb7968Sbouyer  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23*6bdb7968Sbouyer  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24*6bdb7968Sbouyer  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25*6bdb7968Sbouyer  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26*6bdb7968Sbouyer  * SUCH DAMAGE.
27*6bdb7968Sbouyer  */
28*6bdb7968Sbouyer 
29*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_REG		0x00
30*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_FIRSTCONV_MASK		__BITS(31,24)
31*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_FIRSTCONV_SHIFT		24
32*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_CHAN_MASK		__BITS(23,22)
33*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_CHAN_SHIFT		22
34*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_CONT_MASK		__BITS(19,16)
35*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_CONT_SHIFT		16
36*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_KMODE_MASK		__BITS(13,12)
37*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_KMODE_NORMAL		(0 << 12)
38*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_KMODE_SINGLE		(1 << 12)
39*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_KMODE_CONTINUE		(2 << 12)
40*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LV_A_B_CNT_MASK		__BITS(11,8)
41*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LV_A_B_CNT_SHIFT	8
42*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_HOLD_EN			__BIT(6)
43*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LEVEL_B_MASK		__BITS(5,4)
44*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LEVEL_B_3C		(0 << 4)
45*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LEVEL_B_39		(1 << 4)
46*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LEVEL_B_36		(2 << 4)
47*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_LEVEL_B_33		(3 << 4)
48*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_RATE_MASK		__BITS(3,2)
49*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_RATE_250		(0 << 2)
50*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_RATE_125		(1 << 2)
51*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_RATE_62			(2 << 2)
52*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_RATE_31			(3 << 2)
53*6bdb7968Sbouyer #define AWIN_LRADC_CTRL_EN			__BIT(0)
54*6bdb7968Sbouyer #define AWIN_LRADC_INTC_REG		0x04
55*6bdb7968Sbouyer #define AWIN_LRADC_INTS_REG		0x08
56*6bdb7968Sbouyer #define AWIN_LRADC_INT_KEYUP1		__BIT(12)
57*6bdb7968Sbouyer #define AWIN_LRADC_INT_ALREADYHOLD1	__BIT(11)
58*6bdb7968Sbouyer #define AWIN_LRADC_INT_HOLD1		__BIT(10)
59*6bdb7968Sbouyer #define AWIN_LRADC_INT_KEY1		__BIT(9)
60*6bdb7968Sbouyer #define AWIN_LRADC_INT_DATA1		__BIT(8)
61*6bdb7968Sbouyer #define AWIN_LRADC_INT_KEYUP0		__BIT(4)
62*6bdb7968Sbouyer #define AWIN_LRADC_INT_ALREADYHOLD0	__BIT(3)
63*6bdb7968Sbouyer #define AWIN_LRADC_INT_HOLD0		__BIT(2)
64*6bdb7968Sbouyer #define AWIN_LRADC_INT_KEY0		__BIT(1)
65*6bdb7968Sbouyer #define AWIN_LRADC_INT_DATA0		__BIT(0)
66*6bdb7968Sbouyer #define AWIN_LRADC_DATA0_REG		0x0c
67*6bdb7968Sbouyer #define AWIN_LRADC_DATA1_REG		0x10
68*6bdb7968Sbouyer 
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