1*a5198ca0Sjmcneill /* $NetBSD: sun8i_h3_r_ccu.h,v 1.1 2017/09/30 12:48:58 jmcneill Exp $ */ 2*a5198ca0Sjmcneill 3*a5198ca0Sjmcneill /*- 4*a5198ca0Sjmcneill * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5*a5198ca0Sjmcneill * All rights reserved. 6*a5198ca0Sjmcneill * 7*a5198ca0Sjmcneill * Redistribution and use in source and binary forms, with or without 8*a5198ca0Sjmcneill * modification, are permitted provided that the following conditions 9*a5198ca0Sjmcneill * are met: 10*a5198ca0Sjmcneill * 1. Redistributions of source code must retain the above copyright 11*a5198ca0Sjmcneill * notice, this list of conditions and the following disclaimer. 12*a5198ca0Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 13*a5198ca0Sjmcneill * notice, this list of conditions and the following disclaimer in the 14*a5198ca0Sjmcneill * documentation and/or other materials provided with the distribution. 15*a5198ca0Sjmcneill * 16*a5198ca0Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*a5198ca0Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*a5198ca0Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*a5198ca0Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*a5198ca0Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21*a5198ca0Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*a5198ca0Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23*a5198ca0Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24*a5198ca0Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*a5198ca0Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*a5198ca0Sjmcneill * SUCH DAMAGE. 27*a5198ca0Sjmcneill */ 28*a5198ca0Sjmcneill 29*a5198ca0Sjmcneill #ifndef _ARM_SUN8I_H3_R_CCU_H 30*a5198ca0Sjmcneill #define _ARM_SUN8I_H3_R_CCU_H 31*a5198ca0Sjmcneill 32*a5198ca0Sjmcneill #define H3_R_RST_APB0_IR 0 33*a5198ca0Sjmcneill #define H3_R_RST_APB0_TIMER 1 34*a5198ca0Sjmcneill #define H3_R_RST_APB0_RSB 2 35*a5198ca0Sjmcneill #define H3_R_RST_APB0_UART 3 36*a5198ca0Sjmcneill #define H3_R_RST_APB0_I2C 5 37*a5198ca0Sjmcneill 38*a5198ca0Sjmcneill #define H3_R_CLK_AR100 0 39*a5198ca0Sjmcneill #define H3_R_CLK_AHB0 1 40*a5198ca0Sjmcneill #define H3_R_CLK_APB0 2 41*a5198ca0Sjmcneill #define H3_R_CLK_APB0_PIO 3 42*a5198ca0Sjmcneill #define H3_R_CLK_APB0_IR 4 43*a5198ca0Sjmcneill #define H3_R_CLK_APB0_TIMER 5 44*a5198ca0Sjmcneill #define H3_R_CLK_APB0_RSB 6 45*a5198ca0Sjmcneill #define H3_R_CLK_APB0_UART 7 46*a5198ca0Sjmcneill #define H3_R_CLK_APB0_I2C 9 47*a5198ca0Sjmcneill #define H3_R_CLK_APB0_TWD 10 48*a5198ca0Sjmcneill #define H3_R_CLK_IR 11 49*a5198ca0Sjmcneill 50*a5198ca0Sjmcneill #endif /* _ARM_SUN8I_H3_R_CCU_H */ 51