1*47219325Sjmcneill /* $NetBSD: sun50i_a64_r_ccu.h,v 1.1 2018/05/05 09:54:53 jmcneill Exp $ */ 2*47219325Sjmcneill 3*47219325Sjmcneill /*- 4*47219325Sjmcneill * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5*47219325Sjmcneill * All rights reserved. 6*47219325Sjmcneill * 7*47219325Sjmcneill * Redistribution and use in source and binary forms, with or without 8*47219325Sjmcneill * modification, are permitted provided that the following conditions 9*47219325Sjmcneill * are met: 10*47219325Sjmcneill * 1. Redistributions of source code must retain the above copyright 11*47219325Sjmcneill * notice, this list of conditions and the following disclaimer. 12*47219325Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 13*47219325Sjmcneill * notice, this list of conditions and the following disclaimer in the 14*47219325Sjmcneill * documentation and/or other materials provided with the distribution. 15*47219325Sjmcneill * 16*47219325Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*47219325Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*47219325Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*47219325Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*47219325Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21*47219325Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*47219325Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23*47219325Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24*47219325Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*47219325Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*47219325Sjmcneill * SUCH DAMAGE. 27*47219325Sjmcneill */ 28*47219325Sjmcneill 29*47219325Sjmcneill #ifndef _ARM_SUN50I_A64_R_CCU_H 30*47219325Sjmcneill #define _ARM_SUN50I_A64_R_CCU_H 31*47219325Sjmcneill 32*47219325Sjmcneill #define A64_R_RST_APB0_IR 0 33*47219325Sjmcneill #define A64_R_RST_APB0_TIMER 1 34*47219325Sjmcneill #define A64_R_RST_APB0_RSB 2 35*47219325Sjmcneill #define A64_R_RST_APB0_UART 3 36*47219325Sjmcneill #define A64_R_RST_APB0_I2C 5 37*47219325Sjmcneill 38*47219325Sjmcneill #define A64_R_CLK_AR100 0 39*47219325Sjmcneill #define A64_R_CLK_AHB0 1 40*47219325Sjmcneill #define A64_R_CLK_APB0 2 41*47219325Sjmcneill #define A64_R_CLK_APB0_PIO 3 42*47219325Sjmcneill #define A64_R_CLK_APB0_IR 4 43*47219325Sjmcneill #define A64_R_CLK_APB0_TIMER 5 44*47219325Sjmcneill #define A64_R_CLK_APB0_RSB 6 45*47219325Sjmcneill #define A64_R_CLK_APB0_UART 7 46*47219325Sjmcneill #define A64_R_CLK_APB0_I2C 9 47*47219325Sjmcneill #define A64_R_CLK_APB0_TWD 10 48*47219325Sjmcneill #define A64_R_CLK_IR 11 49*47219325Sjmcneill 50*47219325Sjmcneill #endif /* _ARM_SUN50I_A64_R_CCU_H */ 51