1*0c019004Sjmcneill /* $NetBSD: sun50i_a64_ccu.h,v 1.1 2017/09/07 01:07:04 jmcneill Exp $ */ 2*0c019004Sjmcneill 3*0c019004Sjmcneill /*- 4*0c019004Sjmcneill * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5*0c019004Sjmcneill * All rights reserved. 6*0c019004Sjmcneill * 7*0c019004Sjmcneill * Redistribution and use in source and binary forms, with or without 8*0c019004Sjmcneill * modification, are permitted provided that the following conditions 9*0c019004Sjmcneill * are met: 10*0c019004Sjmcneill * 1. Redistributions of source code must retain the above copyright 11*0c019004Sjmcneill * notice, this list of conditions and the following disclaimer. 12*0c019004Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 13*0c019004Sjmcneill * notice, this list of conditions and the following disclaimer in the 14*0c019004Sjmcneill * documentation and/or other materials provided with the distribution. 15*0c019004Sjmcneill * 16*0c019004Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*0c019004Sjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*0c019004Sjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*0c019004Sjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*0c019004Sjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21*0c019004Sjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*0c019004Sjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23*0c019004Sjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24*0c019004Sjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*0c019004Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*0c019004Sjmcneill * SUCH DAMAGE. 27*0c019004Sjmcneill */ 28*0c019004Sjmcneill 29*0c019004Sjmcneill #ifndef _SUN50I_A64_CCU_H 30*0c019004Sjmcneill #define _SUN50I_A64_CCU_H 31*0c019004Sjmcneill 32*0c019004Sjmcneill #define A64_RST_USB_PHY0 0 33*0c019004Sjmcneill #define A64_RST_USB_PHY1 1 34*0c019004Sjmcneill #define A64_RST_USB_HSIC 2 35*0c019004Sjmcneill #define A64_RST_DRAM 3 36*0c019004Sjmcneill #define A64_RST_MBUS 4 37*0c019004Sjmcneill #define A64_RST_BUS_MIPI_DSI 5 38*0c019004Sjmcneill #define A64_RST_BUS_CE 6 39*0c019004Sjmcneill #define A64_RST_BUS_DMA 7 40*0c019004Sjmcneill #define A64_RST_BUS_MMC0 8 41*0c019004Sjmcneill #define A64_RST_BUS_MMC1 9 42*0c019004Sjmcneill #define A64_RST_BUS_MMC2 10 43*0c019004Sjmcneill #define A64_RST_BUS_NAND 11 44*0c019004Sjmcneill #define A64_RST_BUS_DRAM 12 45*0c019004Sjmcneill #define A64_RST_BUS_EMAC 13 46*0c019004Sjmcneill #define A64_RST_BUS_TS 14 47*0c019004Sjmcneill #define A64_RST_BUS_HSTIMER 15 48*0c019004Sjmcneill #define A64_RST_BUS_SPI0 16 49*0c019004Sjmcneill #define A64_RST_BUS_SPI1 17 50*0c019004Sjmcneill #define A64_RST_BUS_OTG 18 51*0c019004Sjmcneill #define A64_RST_BUS_EHCI0 19 52*0c019004Sjmcneill #define A64_RST_BUS_EHCI1 20 53*0c019004Sjmcneill #define A64_RST_BUS_OHCI0 21 54*0c019004Sjmcneill #define A64_RST_BUS_OHCI1 22 55*0c019004Sjmcneill #define A64_RST_BUS_VE 23 56*0c019004Sjmcneill #define A64_RST_BUS_TCON0 24 57*0c019004Sjmcneill #define A64_RST_BUS_TCON1 25 58*0c019004Sjmcneill #define A64_RST_BUS_DEINTERLACE 26 59*0c019004Sjmcneill #define A64_RST_BUS_CSI 27 60*0c019004Sjmcneill #define A64_RST_BUS_HDMI0 28 61*0c019004Sjmcneill #define A64_RST_BUS_HDMI1 29 62*0c019004Sjmcneill #define A64_RST_BUS_DE 30 63*0c019004Sjmcneill #define A64_RST_BUS_GPU 31 64*0c019004Sjmcneill #define A64_RST_BUS_MSGBOX 32 65*0c019004Sjmcneill #define A64_RST_BUS_SPINLOCK 33 66*0c019004Sjmcneill #define A64_RST_BUS_DBG 34 67*0c019004Sjmcneill #define A64_RST_BUS_LVDS 35 68*0c019004Sjmcneill #define A64_RST_BUS_CODEC 36 69*0c019004Sjmcneill #define A64_RST_BUS_SPDIF 37 70*0c019004Sjmcneill #define A64_RST_BUS_THS 38 71*0c019004Sjmcneill #define A64_RST_BUS_I2S0 39 72*0c019004Sjmcneill #define A64_RST_BUS_I2S1 40 73*0c019004Sjmcneill #define A64_RST_BUS_I2S2 41 74*0c019004Sjmcneill #define A64_RST_BUS_I2C0 42 75*0c019004Sjmcneill #define A64_RST_BUS_I2C1 43 76*0c019004Sjmcneill #define A64_RST_BUS_I2C2 44 77*0c019004Sjmcneill #define A64_RST_BUS_SCR 45 78*0c019004Sjmcneill #define A64_RST_BUS_UART0 46 79*0c019004Sjmcneill #define A64_RST_BUS_UART1 47 80*0c019004Sjmcneill #define A64_RST_BUS_UART2 48 81*0c019004Sjmcneill #define A64_RST_BUS_UART3 49 82*0c019004Sjmcneill #define A64_RST_BUS_UART4 50 83*0c019004Sjmcneill 84*0c019004Sjmcneill #define A64_CLK_OSC_12M 0 85*0c019004Sjmcneill #define A64_CLK_PLL_CPUX 1 86*0c019004Sjmcneill #define A64_CLK_PLL_AUDIO_BASE 2 87*0c019004Sjmcneill #define A64_CLK_PLL_AUDIO 3 88*0c019004Sjmcneill #define A64_CLK_PLL_AUDIO_2X 4 89*0c019004Sjmcneill #define A64_CLK_PLL_AUDIO_4X 5 90*0c019004Sjmcneill #define A64_CLK_PLL_AUDIO_8X 6 91*0c019004Sjmcneill #define A64_CLK_PLL_VIDEO0 7 92*0c019004Sjmcneill #define A64_CLK_PLL_VIDEO0_2X 8 93*0c019004Sjmcneill #define A64_CLK_PLL_VE 9 94*0c019004Sjmcneill #define A64_CLK_PLL_DDR0 10 95*0c019004Sjmcneill #define A64_CLK_PLL_PERIPH0 11 96*0c019004Sjmcneill #define A64_CLK_PLL_PERIPH0_2X 12 97*0c019004Sjmcneill #define A64_CLK_PLL_PERIPH1 13 98*0c019004Sjmcneill #define A64_CLK_PLL_PERIPH1_2X 14 99*0c019004Sjmcneill #define A64_CLK_PLL_VIDEO1 15 100*0c019004Sjmcneill #define A64_CLK_PLL_GPU 16 101*0c019004Sjmcneill #define A64_CLK_PLL_MIPI 17 102*0c019004Sjmcneill #define A64_CLK_PLL_HSIC 18 103*0c019004Sjmcneill #define A64_CLK_PLL_DE 19 104*0c019004Sjmcneill #define A64_CLK_PLL_DDR1 20 105*0c019004Sjmcneill #define A64_CLK_CPUX 21 106*0c019004Sjmcneill #define A64_CLK_AXI 22 107*0c019004Sjmcneill #define A64_CLK_APB 23 108*0c019004Sjmcneill #define A64_CLK_AHB1 24 109*0c019004Sjmcneill #define A64_CLK_APB1 25 110*0c019004Sjmcneill #define A64_CLK_APB2 26 111*0c019004Sjmcneill #define A64_CLK_AHB2 27 112*0c019004Sjmcneill #define A64_CLK_BUS_MIPI_DSI 28 113*0c019004Sjmcneill #define A64_CLK_BUS_CE 29 114*0c019004Sjmcneill #define A64_CLK_BUS_DMA 30 115*0c019004Sjmcneill #define A64_CLK_BUS_MMC0 31 116*0c019004Sjmcneill #define A64_CLK_BUS_MMC1 32 117*0c019004Sjmcneill #define A64_CLK_BUS_MMC2 33 118*0c019004Sjmcneill #define A64_CLK_BUS_NAND 34 119*0c019004Sjmcneill #define A64_CLK_BUS_DRAM 35 120*0c019004Sjmcneill #define A64_CLK_BUS_EMAC 36 121*0c019004Sjmcneill #define A64_CLK_BUS_TS 37 122*0c019004Sjmcneill #define A64_CLK_BUS_HSTIMER 38 123*0c019004Sjmcneill #define A64_CLK_BUS_SPI0 39 124*0c019004Sjmcneill #define A64_CLK_BUS_SPI1 40 125*0c019004Sjmcneill #define A64_CLK_BUS_OTG 41 126*0c019004Sjmcneill #define A64_CLK_BUS_EHCI0 42 127*0c019004Sjmcneill #define A64_CLK_BUS_EHCI1 43 128*0c019004Sjmcneill #define A64_CLK_BUS_OHCI0 44 129*0c019004Sjmcneill #define A64_CLK_BUS_OHCI1 45 130*0c019004Sjmcneill #define A64_CLK_BUS_VE 46 131*0c019004Sjmcneill #define A64_CLK_BUS_TCON0 47 132*0c019004Sjmcneill #define A64_CLK_BUS_TCON1 48 133*0c019004Sjmcneill #define A64_CLK_BUS_DEINTERLACE 49 134*0c019004Sjmcneill #define A64_CLK_BUS_CSI 50 135*0c019004Sjmcneill #define A64_CLK_BUS_HDMI 51 136*0c019004Sjmcneill #define A64_CLK_BUS_DE 52 137*0c019004Sjmcneill #define A64_CLK_BUS_GPU 53 138*0c019004Sjmcneill #define A64_CLK_BUS_MSGBOX 54 139*0c019004Sjmcneill #define A64_CLK_BUS_SPINLOCK 55 140*0c019004Sjmcneill #define A64_CLK_BUS_CODEC 56 141*0c019004Sjmcneill #define A64_CLK_BUS_SPDIF 57 142*0c019004Sjmcneill #define A64_CLK_BUS_PIO 58 143*0c019004Sjmcneill #define A64_CLK_BUS_THS 59 144*0c019004Sjmcneill #define A64_CLK_BUS_I2S0 60 145*0c019004Sjmcneill #define A64_CLK_BUS_I2S1 61 146*0c019004Sjmcneill #define A64_CLK_BUS_I2S2 62 147*0c019004Sjmcneill #define A64_CLK_BUS_I2C0 63 148*0c019004Sjmcneill #define A64_CLK_BUS_I2C1 64 149*0c019004Sjmcneill #define A64_CLK_BUS_I2C2 65 150*0c019004Sjmcneill #define A64_CLK_BUS_SCR 66 151*0c019004Sjmcneill #define A64_CLK_BUS_UART0 67 152*0c019004Sjmcneill #define A64_CLK_BUS_UART1 68 153*0c019004Sjmcneill #define A64_CLK_BUS_UART2 69 154*0c019004Sjmcneill #define A64_CLK_BUS_UART3 70 155*0c019004Sjmcneill #define A64_CLK_BUS_UART4 71 156*0c019004Sjmcneill #define A64_CLK_BUS_DBG 72 157*0c019004Sjmcneill #define A64_CLK_THS 73 158*0c019004Sjmcneill #define A64_CLK_NAND 74 159*0c019004Sjmcneill #define A64_CLK_MMC0 75 160*0c019004Sjmcneill #define A64_CLK_MMC1 76 161*0c019004Sjmcneill #define A64_CLK_MMC2 77 162*0c019004Sjmcneill #define A64_CLK_TS 78 163*0c019004Sjmcneill #define A64_CLK_CE 79 164*0c019004Sjmcneill #define A64_CLK_SPI0 80 165*0c019004Sjmcneill #define A64_CLK_SPI1 81 166*0c019004Sjmcneill #define A64_CLK_I2S0 82 167*0c019004Sjmcneill #define A64_CLK_I2S1 83 168*0c019004Sjmcneill #define A64_CLK_I2S2 84 169*0c019004Sjmcneill #define A64_CLK_SPDIF 85 170*0c019004Sjmcneill #define A64_CLK_USB_PHY0 86 171*0c019004Sjmcneill #define A64_CLK_USB_PHY1 87 172*0c019004Sjmcneill #define A64_CLK_USB_HSIC 88 173*0c019004Sjmcneill #define A64_CLK_USB_HSIC_12M 89 174*0c019004Sjmcneill #define A64_CLK_USB_OHCI0_12M 90 175*0c019004Sjmcneill #define A64_CLK_USB_OHCI0 91 176*0c019004Sjmcneill #define A64_CLK_USB_OHCI1_12M 92 177*0c019004Sjmcneill #define A64_CLK_USB_OHCI1 93 178*0c019004Sjmcneill #define A64_CLK_DRAM 94 179*0c019004Sjmcneill #define A64_CLK_DRAM_VE 95 180*0c019004Sjmcneill #define A64_CLK_DRAM_CSI 96 181*0c019004Sjmcneill #define A64_CLK_DRAM_DEINTERLACE 97 182*0c019004Sjmcneill #define A64_CLK_DRAM_TS 98 183*0c019004Sjmcneill #define A64_CLK_DE 99 184*0c019004Sjmcneill #define A64_CLK_TCON0 100 185*0c019004Sjmcneill #define A64_CLK_TCON1 101 186*0c019004Sjmcneill #define A64_CLK_DEINTERLACE 102 187*0c019004Sjmcneill #define A64_CLK_CSI_MISC 103 188*0c019004Sjmcneill #define A64_CLK_CSI_SCLK 104 189*0c019004Sjmcneill #define A64_CLK_CSI_MCLK 105 190*0c019004Sjmcneill #define A64_CLK_VE 106 191*0c019004Sjmcneill #define A64_CLK_AC_DIG 107 192*0c019004Sjmcneill #define A64_CLK_AC_DIG_4X 108 193*0c019004Sjmcneill #define A64_CLK_AVS 109 194*0c019004Sjmcneill #define A64_CLK_HDMI 110 195*0c019004Sjmcneill #define A64_CLK_HDMI_DDC 111 196*0c019004Sjmcneill #define A64_CLK_MBUS 112 197*0c019004Sjmcneill #define A64_CLK_DSI_DPHY 113 198*0c019004Sjmcneill #define A64_CLK_GPU 114 199*0c019004Sjmcneill 200*0c019004Sjmcneill #endif /* !_SUN50I_A64_CCU_H */ 201