xref: /netbsd-src/sys/arch/arm/pci/pci_smccc.c (revision 53a7ab421c95689922501594407bcbf263dca41f)
1*53a7ab42Sjmcneill /* $NetBSD: pci_smccc.c,v 1.1 2021/08/07 21:23:37 jmcneill Exp $ */
2*53a7ab42Sjmcneill 
3*53a7ab42Sjmcneill /*-
4*53a7ab42Sjmcneill  * Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca>
5*53a7ab42Sjmcneill  * All rights reserved.
6*53a7ab42Sjmcneill  *
7*53a7ab42Sjmcneill  * Redistribution and use in source and binary forms, with or without
8*53a7ab42Sjmcneill  * modification, are permitted provided that the following conditions
9*53a7ab42Sjmcneill  * are met:
10*53a7ab42Sjmcneill  * 1. Redistributions of source code must retain the above copyright
11*53a7ab42Sjmcneill  *    notice, this list of conditions and the following disclaimer.
12*53a7ab42Sjmcneill  * 2. Redistributions in binary form must reproduce the above copyright
13*53a7ab42Sjmcneill  *    notice, this list of conditions and the following disclaimer in the
14*53a7ab42Sjmcneill  *    documentation and/or other materials provided with the distribution.
15*53a7ab42Sjmcneill  *
16*53a7ab42Sjmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17*53a7ab42Sjmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18*53a7ab42Sjmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19*53a7ab42Sjmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20*53a7ab42Sjmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21*53a7ab42Sjmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22*53a7ab42Sjmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23*53a7ab42Sjmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24*53a7ab42Sjmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25*53a7ab42Sjmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26*53a7ab42Sjmcneill  * SUCH DAMAGE.
27*53a7ab42Sjmcneill  */
28*53a7ab42Sjmcneill 
29*53a7ab42Sjmcneill #include <sys/cdefs.h>
30*53a7ab42Sjmcneill __KERNEL_RCSID(0, "$NetBSD: pci_smccc.c,v 1.1 2021/08/07 21:23:37 jmcneill Exp $");
31*53a7ab42Sjmcneill 
32*53a7ab42Sjmcneill #include <sys/param.h>
33*53a7ab42Sjmcneill #include <sys/kernel.h>
34*53a7ab42Sjmcneill 
35*53a7ab42Sjmcneill #include <arm/arm/smccc.h>
36*53a7ab42Sjmcneill #include <arm/pci/pci_smccc.h>
37*53a7ab42Sjmcneill 
38*53a7ab42Sjmcneill /* Minimum SMCCC version required for PCI_VERSION call. */
39*53a7ab42Sjmcneill #define	SMCCC_VERSION_1_1	0x10001
40*53a7ab42Sjmcneill 
41*53a7ab42Sjmcneill /* PCI Configuration Space Access ABI functions */
42*53a7ab42Sjmcneill #define	PCI_VERSION		0x84000130
43*53a7ab42Sjmcneill #define	PCI_FEATURES		0x84000131
44*53a7ab42Sjmcneill #define	PCI_READ		0x84000132
45*53a7ab42Sjmcneill #define	PCI_WRITE		0x84000133
46*53a7ab42Sjmcneill #define	PCI_GET_SEG_INFO	0x84000134
47*53a7ab42Sjmcneill #define	 GET_SEG_INFO_BUS_START		__BITS(7,0)
48*53a7ab42Sjmcneill #define	 GET_SEG_INFO_BUS_END		__BITS(15,8)
49*53a7ab42Sjmcneill 
50*53a7ab42Sjmcneill static int
pci_smccc_call(uint32_t fid,register_t arg1,register_t arg2,register_t arg3,register_t arg4,register_t * res0,register_t * res1,register_t * res2,register_t * res3)51*53a7ab42Sjmcneill pci_smccc_call(uint32_t fid,
52*53a7ab42Sjmcneill     register_t arg1, register_t arg2, register_t arg3, register_t arg4,
53*53a7ab42Sjmcneill     register_t *res0, register_t *res1, register_t *res2, register_t *res3)
54*53a7ab42Sjmcneill {
55*53a7ab42Sjmcneill 	static int smccc_ver;
56*53a7ab42Sjmcneill 
57*53a7ab42Sjmcneill 	if (smccc_ver == 0) {
58*53a7ab42Sjmcneill 		smccc_ver = smccc_version();
59*53a7ab42Sjmcneill 	}
60*53a7ab42Sjmcneill 	if (smccc_ver < SMCCC_VERSION_1_1) {
61*53a7ab42Sjmcneill 		return SMCCC_NOT_SUPPORTED;
62*53a7ab42Sjmcneill 	}
63*53a7ab42Sjmcneill 
64*53a7ab42Sjmcneill 	return smccc_call(fid, arg1, arg2, arg3, arg4,
65*53a7ab42Sjmcneill 			  res0, res1, res2, res3);
66*53a7ab42Sjmcneill }
67*53a7ab42Sjmcneill 
68*53a7ab42Sjmcneill int
pci_smccc_version(void)69*53a7ab42Sjmcneill pci_smccc_version(void)
70*53a7ab42Sjmcneill {
71*53a7ab42Sjmcneill 	return pci_smccc_call(PCI_VERSION, 0, 0, 0, 0,
72*53a7ab42Sjmcneill 			      NULL, NULL, NULL, NULL);
73*53a7ab42Sjmcneill }
74*53a7ab42Sjmcneill 
75*53a7ab42Sjmcneill int
pci_smccc_features(uint32_t fid)76*53a7ab42Sjmcneill pci_smccc_features(uint32_t fid)
77*53a7ab42Sjmcneill {
78*53a7ab42Sjmcneill 	return pci_smccc_call(PCI_FEATURES, fid, 0, 0, 0,
79*53a7ab42Sjmcneill 			      NULL, NULL, NULL, NULL);
80*53a7ab42Sjmcneill }
81*53a7ab42Sjmcneill 
82*53a7ab42Sjmcneill int
pci_smccc_read(uint32_t sbdf,uint32_t offset,uint32_t access_size,uint32_t * data)83*53a7ab42Sjmcneill pci_smccc_read(uint32_t sbdf, uint32_t offset, uint32_t access_size,
84*53a7ab42Sjmcneill     uint32_t *data)
85*53a7ab42Sjmcneill {
86*53a7ab42Sjmcneill 	register_t value;
87*53a7ab42Sjmcneill 	int status;
88*53a7ab42Sjmcneill 
89*53a7ab42Sjmcneill 	status = pci_smccc_call(PCI_READ, sbdf, offset, access_size, 0,
90*53a7ab42Sjmcneill 				NULL, &value, NULL, NULL);
91*53a7ab42Sjmcneill 	if (status == SMCCC_SUCCESS) {
92*53a7ab42Sjmcneill 		*data = value;
93*53a7ab42Sjmcneill 	}
94*53a7ab42Sjmcneill 
95*53a7ab42Sjmcneill 	return status;
96*53a7ab42Sjmcneill }
97*53a7ab42Sjmcneill 
98*53a7ab42Sjmcneill int
pci_smccc_write(uint32_t sbdf,uint32_t offset,uint32_t access_size,uint32_t data)99*53a7ab42Sjmcneill pci_smccc_write(uint32_t sbdf, uint32_t offset, uint32_t access_size,
100*53a7ab42Sjmcneill     uint32_t data)
101*53a7ab42Sjmcneill {
102*53a7ab42Sjmcneill 	return pci_smccc_call(PCI_WRITE, sbdf, offset, access_size, data,
103*53a7ab42Sjmcneill 			      NULL, NULL, NULL, NULL);
104*53a7ab42Sjmcneill }
105*53a7ab42Sjmcneill 
106*53a7ab42Sjmcneill int
pci_smccc_get_seg_info(uint16_t seg,uint8_t * bus_start,uint8_t * bus_end,uint16_t * next_seg)107*53a7ab42Sjmcneill pci_smccc_get_seg_info(uint16_t seg, uint8_t *bus_start, uint8_t *bus_end,
108*53a7ab42Sjmcneill     uint16_t *next_seg)
109*53a7ab42Sjmcneill {
110*53a7ab42Sjmcneill 	register_t res1, res2;
111*53a7ab42Sjmcneill 	int status;
112*53a7ab42Sjmcneill 
113*53a7ab42Sjmcneill 	status = pci_smccc_call(PCI_GET_SEG_INFO, seg, 0, 0, 0,
114*53a7ab42Sjmcneill 				NULL, &res1, &res2, NULL);
115*53a7ab42Sjmcneill 	if (status == SMCCC_SUCCESS) {
116*53a7ab42Sjmcneill 		*bus_start = __SHIFTOUT(res1, GET_SEG_INFO_BUS_START);
117*53a7ab42Sjmcneill 		*bus_end = __SHIFTOUT(res1, GET_SEG_INFO_BUS_END);
118*53a7ab42Sjmcneill 		*next_seg = (uint16_t)res2;
119*53a7ab42Sjmcneill 	}
120*53a7ab42Sjmcneill 
121*53a7ab42Sjmcneill 	return status;
122*53a7ab42Sjmcneill }
123