1*a33a6c43Sbouyer /* $NetBSD: imx6_spi.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $ */
28644267aSskrll
38644267aSskrll /*-
48644267aSskrll * Copyright (c) 2019 Genetec Corporation. All rights reserved.
58644267aSskrll * Written by Hashimoto Kenichi for Genetec Corporation.
68644267aSskrll *
78644267aSskrll * Redistribution and use in source and binary forms, with or without
88644267aSskrll * modification, are permitted provided that the following conditions
98644267aSskrll * are met:
108644267aSskrll * 1. Redistributions of source code must retain the above copyright
118644267aSskrll * notice, this list of conditions and the following disclaimer.
128644267aSskrll * 2. Redistributions in binary form must reproduce the above copyright
138644267aSskrll * notice, this list of conditions and the following disclaimer in the
148644267aSskrll * documentation and/or other materials provided with the distribution.
158644267aSskrll *
168644267aSskrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
178644267aSskrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
188644267aSskrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
198644267aSskrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
208644267aSskrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
218644267aSskrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
228644267aSskrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
238644267aSskrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
248644267aSskrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
258644267aSskrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
268644267aSskrll * SUCH DAMAGE.
278644267aSskrll */
288644267aSskrll
298644267aSskrll #include <sys/cdefs.h>
30*a33a6c43Sbouyer __KERNEL_RCSID(0, "$NetBSD: imx6_spi.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $");
318644267aSskrll
328644267aSskrll #include "opt_imxspi.h"
338644267aSskrll
348644267aSskrll #include <sys/param.h>
358644267aSskrll #include <sys/bus.h>
368644267aSskrll #include <sys/device.h>
378644267aSskrll #include <sys/kmem.h>
388644267aSskrll #include <sys/gpio.h>
398644267aSskrll
408644267aSskrll #include <arm/imx/imxspivar.h>
418644267aSskrll
428644267aSskrll #include <dev/fdt/fdtvar.h>
438644267aSskrll
448644267aSskrll struct imxspi_fdt_softc {
458644267aSskrll struct imxspi_softc sc_imxspi; /* Must be first */
468644267aSskrll
478644267aSskrll struct spi_chipset_tag sc_tag;
488644267aSskrll struct clk *sc_clk;
498644267aSskrll
508644267aSskrll struct fdtbus_gpio_pin **sc_pin_cs;
518644267aSskrll };
528644267aSskrll
538644267aSskrll struct imx_spi_config {
548644267aSskrll bool enhanced;
558644267aSskrll enum imxspi_type type;
568644267aSskrll };
578644267aSskrll
588644267aSskrll static const struct imx_spi_config imx6q_spi_config = {
598644267aSskrll .enhanced = true,
608644267aSskrll .type = IMX51_ECSPI,
618644267aSskrll };
628644267aSskrll
63646c0f59Sthorpej static const struct device_compatible_entry compat_data[] = {
64646c0f59Sthorpej { .compat = "fsl,imx6q-ecspi", .data = &imx6q_spi_config },
65*a33a6c43Sbouyer { .compat = "fsl,imx6sx-ecspi", .data = &imx6q_spi_config },
66ec189949Sthorpej DEVICE_COMPAT_EOL
678644267aSskrll };
688644267aSskrll
698644267aSskrll CFATTACH_DECL_NEW(imxspi_fdt, sizeof(struct imxspi_fdt_softc),
708644267aSskrll imxspi_match, imxspi_attach, NULL, NULL);
718644267aSskrll
728644267aSskrll static int
imxspi_cs_enable(void * arg,int slave)738644267aSskrll imxspi_cs_enable(void *arg, int slave)
748644267aSskrll {
758644267aSskrll struct imxspi_fdt_softc * const sc = arg;
768644267aSskrll fdtbus_gpio_write(sc->sc_pin_cs[slave], 1);
778644267aSskrll return 0;
788644267aSskrll }
798644267aSskrll
808644267aSskrll static int
imxspi_cs_disable(void * arg,int slave)818644267aSskrll imxspi_cs_disable(void *arg, int slave)
828644267aSskrll {
838644267aSskrll struct imxspi_fdt_softc * const sc = arg;
848644267aSskrll fdtbus_gpio_write(sc->sc_pin_cs[slave], 0);
858644267aSskrll return 0;
868644267aSskrll }
878644267aSskrll
888644267aSskrll int
imxspi_match(device_t parent,cfdata_t cf,void * aux)898644267aSskrll imxspi_match(device_t parent, cfdata_t cf, void *aux)
908644267aSskrll {
918644267aSskrll struct fdt_attach_args * const faa = aux;
928644267aSskrll
936e54367aSthorpej return of_compatible_match(faa->faa_phandle, compat_data);
948644267aSskrll }
958644267aSskrll
968644267aSskrll void
imxspi_attach(device_t parent,device_t self,void * aux)978644267aSskrll imxspi_attach(device_t parent, device_t self, void *aux)
988644267aSskrll {
998644267aSskrll struct imxspi_fdt_softc * const ifsc = device_private(self);
1008644267aSskrll struct imxspi_softc * const sc = &ifsc->sc_imxspi;
1018644267aSskrll struct fdt_attach_args * const faa = aux;
1028644267aSskrll char intrstr[128];
1038644267aSskrll const int phandle = faa->faa_phandle;
1048644267aSskrll bus_addr_t addr;
1058644267aSskrll bus_size_t size;
1068644267aSskrll int error;
1078644267aSskrll
108c4d8e5dfSskrll aprint_naive("\n");
109c4d8e5dfSskrll aprint_normal(": SPI\n");
110c4d8e5dfSskrll
1118644267aSskrll u_int nslaves;
1128644267aSskrll error = of_getprop_uint32(phandle, "fsl,spi-num-chipselects", &nslaves);
1138644267aSskrll if (error)
1148644267aSskrll nslaves = 4;
1158644267aSskrll
1168644267aSskrll ifsc->sc_pin_cs = kmem_alloc(sizeof(struct fdtbus_gpio_pin *) * nslaves, KM_SLEEP);
1178644267aSskrll
1188644267aSskrll for (int i = 0; i < nslaves; i++) {
1198644267aSskrll ifsc->sc_pin_cs[i] = fdtbus_gpio_acquire_index(phandle, "cs-gpios", i,
1208644267aSskrll GPIO_PIN_OUTPUT);
1218644267aSskrll }
1228644267aSskrll
1238644267aSskrll ifsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
1248644267aSskrll if (ifsc->sc_clk == NULL) {
1258644267aSskrll aprint_error(": couldn't get clock\n");
1268644267aSskrll return;
1278644267aSskrll }
1288644267aSskrll
1298644267aSskrll error = clk_enable(ifsc->sc_clk);
1308644267aSskrll if (error) {
1318644267aSskrll aprint_error_dev(sc->sc_dev, "couldn't enable: %d\n", error);
1328644267aSskrll return;
1338644267aSskrll }
1348644267aSskrll
1358644267aSskrll ifsc->sc_tag.cookie = ifsc;
1368644267aSskrll ifsc->sc_tag.spi_cs_enable = imxspi_cs_enable;
1378644267aSskrll ifsc->sc_tag.spi_cs_disable = imxspi_cs_disable;
1388644267aSskrll
1398644267aSskrll sc->sc_phandle = phandle;
1408644267aSskrll sc->sc_iot = faa->faa_bst;
1418644267aSskrll
142646c0f59Sthorpej const struct imx_spi_config *config =
1436e54367aSthorpej of_compatible_lookup(phandle, compat_data)->data;
1448644267aSskrll sc->sc_enhanced = config->enhanced;
1458644267aSskrll sc->sc_type = config->type;
1468644267aSskrll
1478644267aSskrll sc->sc_nslaves = nslaves;
1488644267aSskrll sc->sc_freq = clk_get_rate(ifsc->sc_clk);
1498644267aSskrll sc->sc_tag = &ifsc->sc_tag;
1508644267aSskrll
1518644267aSskrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
1528644267aSskrll aprint_error(": couldn't get iomux registers\n");
1538644267aSskrll return;
1548644267aSskrll }
1558644267aSskrll
1568644267aSskrll if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) {
1578644267aSskrll aprint_error_dev(sc->sc_dev, "couldn't map registers\n");
1588644267aSskrll return;
1598644267aSskrll }
1608644267aSskrll
1618644267aSskrll if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
1628644267aSskrll aprint_error_dev(self, "failed to decode interrupt\n");
1638644267aSskrll return;
1648644267aSskrll }
1658644267aSskrll
16682b8374aSjmcneill sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
16782b8374aSjmcneill 0, imxspi_intr, &ifsc->sc_imxspi, device_xname(self));
1688644267aSskrll if (sc->sc_ih == NULL) {
1698644267aSskrll aprint_error_dev(self, "couldn't establish interrupt on %s\n",
1708644267aSskrll intrstr);
1718644267aSskrll return;
1728644267aSskrll }
1738644267aSskrll aprint_normal_dev(self, "interrupting on %s\n", intrstr);
1748644267aSskrll
1758644267aSskrll imxspi_attach_common(self);
1768644267aSskrll }
177