1*5ea5576aSjakllsch# $NetBSD: files.tegra,v 1.52 2020/08/29 19:06:17 jakllsch Exp $ 2d4fd1143Sjmcneill# 3d4fd1143Sjmcneill# Configuration info for NVIDIA Tegra ARM Peripherals 4d4fd1143Sjmcneill# 5d4fd1143Sjmcneill 681bc83c1Sjmcneillfile arch/arm/nvidia/tegra_platform.c 7095f6375Sjmcneillfile arch/arm/nvidia/tegra_soc.c 8095f6375Sjmcneillfile arch/arm/nvidia/tegra_cpufreq.c 9095f6375Sjmcneill 10095f6375Sjmcneill# Tegra T124 (32-bit K1) support 11c2239868Sjmcneillfile arch/arm/nvidia/soc_tegra124.c soc_tegra124 12095f6375Sjmcneilldevice tegra124cpu 13b7a940d9Sjmcneillattach tegra124cpu at cpu with tegra124_cpu 14c2239868Sjmcneillfile arch/arm/nvidia/tegra124_cpu.c tegra124_cpu 15095f6375Sjmcneill 16d59db8d0Sjmcneill# Interrupt controller 17d59db8d0Sjmcneilldevice tegralic 18d59db8d0Sjmcneillattach tegralic at fdt with tegra_lic 19d59db8d0Sjmcneillfile arch/arm/nvidia/tegra_lic.c tegra_lic 20d59db8d0Sjmcneill 21d4fd1143Sjmcneill# Memory controller 22d4fd1143Sjmcneilldevice tegramc 23d59db8d0Sjmcneillattach tegramc at fdt with tegra_mc 24d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_mc.c tegra_mc 25d4fd1143Sjmcneill 26d4fd1143Sjmcneill# Power management controller 27d4fd1143Sjmcneilldevice tegrapmc 28d59db8d0Sjmcneillattach tegrapmc at fdt with tegra_pmc 29d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_pmc.c tegra_pmc 30d4fd1143Sjmcneill 31b2b0f53cSjmcneill# eFUSE 32b2b0f53cSjmcneilldevice tegrafuse 33d59db8d0Sjmcneillattach tegrafuse at fdt with tegra_fuse 34b2b0f53cSjmcneillfile arch/arm/nvidia/tegra_fuse.c tegra_fuse 35b2b0f53cSjmcneill 3651ecd7ebSjmcneill# Clock and Reset controller (T124) 3793e0bfebSjmcneilldevice tegra124car: clk 3893e0bfebSjmcneillattach tegra124car at fdt with tegra124_car 3993e0bfebSjmcneillfile arch/arm/nvidia/tegra124_car.c tegra124_car 408bcb30daSjmcneill 4151ecd7ebSjmcneill# Clock and Reset controller (T210) 4251ecd7ebSjmcneilldevice tegra210car: clk 4351ecd7ebSjmcneillattach tegra210car at fdt with tegra210_car 4451ecd7ebSjmcneillfile arch/arm/nvidia/tegra210_car.c tegra210_car 4551ecd7ebSjmcneill 4608fb0bfeSjmcneill# GPIO controller 4708fb0bfeSjmcneilldevice tegragpio: gpiobus 48d59db8d0Sjmcneillattach tegragpio at fdt with tegra_gpio 4908fb0bfeSjmcneillfile arch/arm/nvidia/tegra_gpio.c tegra_gpio 5008fb0bfeSjmcneill 51d33dbb16Sjmcneill# Timers 52d33dbb16Sjmcneilldevice tegratimer: sysmon_wdog 53d59db8d0Sjmcneillattach tegratimer at fdt with tegra_timer 54d33dbb16Sjmcneillfile arch/arm/nvidia/tegra_timer.c tegra_timer 55d33dbb16Sjmcneill 56cb68b251Sjmcneill# MPIO / Pinmux 570e6fbb04Sjmcneilldevice tegrapinmux 580e6fbb04Sjmcneillattach tegrapinmux at fdt with tegra_pinmux 590e6fbb04Sjmcneillfile arch/arm/nvidia/tegra_pinmux.c tegra_pinmux 600e6fbb04Sjmcneillfile arch/arm/nvidia/tegra210_pinmux.c tegra_pinmux & soc_tegra210 61cb68b251Sjmcneill 62c10789b9Sjmcneill# APB DMA 63c10789b9Sjmcneilldevice tegraapbdma 64c10789b9Sjmcneillattach tegraapbdma at fdt with tegra_apbdma 65c10789b9Sjmcneillfile arch/arm/nvidia/tegra_apbdma.c tegra_apbdma 66c10789b9Sjmcneill 67a7c423b9Sjmcneill# XUSB PADCTL (common) 68cb241d91Sjmcneillfile arch/arm/nvidia/tegra_xusbpad.c tegra_xusbpad 69314c2faeSjmcneilldefflag opt_tegra.h TEGRA_XUSBPAD_DEBUG 70cb241d91Sjmcneill 71a7c423b9Sjmcneill# XUSB PADCTL (Tegra124) 72496fea9eSjmcneilldevice tegra124xpad: tegra_xusbpad 73496fea9eSjmcneillattach tegra124xpad at fdt with tegra124_xusbpad 74a7c423b9Sjmcneillfile arch/arm/nvidia/tegra124_xusbpad.c tegra124_xusbpad 75a7c423b9Sjmcneill 76a7c423b9Sjmcneill# XUSB PADCTL (Tegra210) 77479a90aaSjmcneilldevice tegra210xpad { }: tegra_xusbpad 78479a90aaSjmcneilldevice tegra210xphy: tegra210xpad 79496fea9eSjmcneillattach tegra210xpad at fdt with tegra210_xusbpad 80479a90aaSjmcneillattach tegra210xphy at tegra210xpad 81a7c423b9Sjmcneillfile arch/arm/nvidia/tegra210_xusbpad.c tegra210_xusbpad 82a7c423b9Sjmcneill 83479a90aaSjmcneill 84d4fd1143Sjmcneill# UART 85d59db8d0Sjmcneillattach com at fdt with tegra_com 86efd05cd7Sskrllfile arch/arm/nvidia/tegra_com.c tegra_com 87d4fd1143Sjmcneill 88520aad95Sjmcneill# I2C 89520aad95Sjmcneilldevice tegrai2c: i2cbus, i2cexec 90d59db8d0Sjmcneillattach tegrai2c at fdt with tegra_i2c 91520aad95Sjmcneillfile arch/arm/nvidia/tegra_i2c.c tegra_i2c 92520aad95Sjmcneill 938827e789Sjmcneill# RTC 948827e789Sjmcneilldevice tegrartc 95d59db8d0Sjmcneillattach tegrartc at fdt with tegra_rtc 968827e789Sjmcneillfile arch/arm/nvidia/tegra_rtc.c tegra_rtc 978827e789Sjmcneill 98d7fd9ef6Sjmcneill# USB PHY 99d7fd9ef6Sjmcneilldevice tegrausbphy 100d59db8d0Sjmcneillattach tegrausbphy at fdt with tegra_usbphy 101d7fd9ef6Sjmcneillfile arch/arm/nvidia/tegra_usbphy.c tegra_usbphy 102d7fd9ef6Sjmcneill 103d4fd1143Sjmcneill# USB 2.0 104d59db8d0Sjmcneillattach ehci at fdt with tegra_ehci 105d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_ehci.c tegra_ehci 106d4fd1143Sjmcneill 10785627b23Sjakllsch# XUSB (USB 3.0) 10815102646Suweattach xhci at fdt with tegra_xusb : firmload 10985627b23Sjakllschfile arch/arm/nvidia/tegra_xusb.c tegra_xusb 11067b89dbeSjmcneilldefflag opt_tegra.h TEGRA_XUSB_DEBUG 111*5ea5576aSjakllschdefflag opt_tegra.h TEGRA124_XUSB_BIN_STATIC 112*5ea5576aSjakllschdefflag opt_tegra.h TEGRA210_XUSB_BIN_STATIC 11385627b23Sjakllsch 114d4fd1143Sjmcneill# SDMMC 115d59db8d0Sjmcneillattach sdhc at fdt with tegra_sdhc 116d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_sdhc.c tegra_sdhc 117d4fd1143Sjmcneill 1180af3fdefSjmcneill# Thermal throttling controller 1190af3fdefSjmcneilldevice tegrasoctherm: sysmon_envsys 120d59db8d0Sjmcneillattach tegrasoctherm at fdt with tegra_soctherm 1210af3fdefSjmcneillfile arch/arm/nvidia/tegra_soctherm.c tegra_soctherm 1220af3fdefSjmcneill 123e1b20f28Sjmcneill# PCIE 124e1b20f28Sjmcneilldevice tegrapcie: pcibus 125d59db8d0Sjmcneillattach tegrapcie at fdt with tegra_pcie 126e1b20f28Sjmcneillfile arch/arm/nvidia/tegra_pcie.c tegra_pcie 127e1b20f28Sjmcneill 128d4fd1143Sjmcneill# SATA 129d59db8d0Sjmcneillattach ahcisata at fdt with tegra_ahcisata 130d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_ahcisata.c tegra_ahcisata 131d4fd1143Sjmcneill 132d4fd1143Sjmcneill# HDA 133d59db8d0Sjmcneillattach hdaudio at fdt with tegra_hdaudio 134d4fd1143Sjmcneillfile arch/arm/nvidia/tegra_hdaudio.c tegra_hdaudio 135d4fd1143Sjmcneill 136ab82ac0eSjmcneill# HDMI CEC 137ab82ac0eSjmcneilldevice tegracec: hdmicecbus 138d59db8d0Sjmcneillattach tegracec at fdt with tegra_cec 139ab82ac0eSjmcneillfile arch/arm/nvidia/tegra_cec.c tegra_cec 140ab82ac0eSjmcneill 141056d7a1bSjmcneill# Display 142056d7a1bSjmcneilldefine tegrafbbus { } 143d59db8d0Sjmcneilldevice tegradrm: drmkms, ddc_read_edid, tegrafbbus 144d59db8d0Sjmcneillattach tegradrm at fdt with tegra_drm 145056d7a1bSjmcneillfile arch/arm/nvidia/tegra_drm.c tegra_drm 146056d7a1bSjmcneillfile arch/arm/nvidia/tegra_drm_mode.c tegra_drm 147056d7a1bSjmcneillfile arch/arm/nvidia/tegra_drm_fb.c tegra_drm 148056d7a1bSjmcneill 149056d7a1bSjmcneill# Framebuffer console 150056d7a1bSjmcneilldevice tegrafb: tegrafbbus, drmfb, wsemuldisplaydev 151056d7a1bSjmcneillattach tegrafb at tegrafbbus with tegra_fb 152056d7a1bSjmcneillfile arch/arm/nvidia/tegra_fb.c tegra_fb 153056d7a1bSjmcneill 154f1428902Sjmcneill# GPU 155e0ffebf2Sjmcneillattach nouveau at fdt with tegra_nouveau 156f1428902Sjmcneillfile arch/arm/nvidia/tegra_nouveau.c tegra_nouveau 157f1428902Sjmcneill 158d4fd1143Sjmcneill# SOC parameters 159d4fd1143Sjmcneilldefflag opt_tegra.h SOC_TEGRAK1 1608c41086dSjmcneilldefflag opt_tegra.h SOC_TEGRAX1 161d4fd1143Sjmcneilldefflag opt_tegra.h SOC_TEGRA124: SOC_TEGRAK1 1628c41086dSjmcneilldefflag opt_tegra.h SOC_TEGRA210: SOC_TEGRAX1 163