148914f07Sbsh /*- 248914f07Sbsh * Copyright (c) 2010 Genetec Corporation. All rights reserved. 348914f07Sbsh * Written by Hiroyuki Bessho for Genetec Corporation. 448914f07Sbsh * 548914f07Sbsh * Redistribution and use in source and binary forms, with or without 648914f07Sbsh * modification, are permitted provided that the following conditions 748914f07Sbsh * are met: 848914f07Sbsh * 1. Redistributions of source code must retain the above copyright 948914f07Sbsh * notice, this list of conditions and the following disclaimer. 1048914f07Sbsh * 2. Redistributions in binary form must reproduce the above 1148914f07Sbsh * copyright notice, this list of conditions and the following 1248914f07Sbsh * disclaimer in the documentation and/or other materials provided 1348914f07Sbsh * with the distribution. 1448914f07Sbsh * 1548914f07Sbsh * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' 1648914f07Sbsh * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1748914f07Sbsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 1848914f07Sbsh * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS 1948914f07Sbsh * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2048914f07Sbsh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2148914f07Sbsh * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 2248914f07Sbsh * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 2348914f07Sbsh * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2448914f07Sbsh * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 2548914f07Sbsh * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2648914f07Sbsh * SUCH DAMAGE. 2748914f07Sbsh */ 2848914f07Sbsh 2948914f07Sbsh /* 30*a4103ccdSryo * Watchdog register definitions for Freescale i.MX31/i.MX51/i.MX6 3148914f07Sbsh * 3248914f07Sbsh * MCIMX31 and MCIMX31L Application Processors 3348914f07Sbsh * Reference Manual 3448914f07Sbsh * MCIMC31RM 3548914f07Sbsh * Rev. 2.3 3648914f07Sbsh * 1/2007 3748914f07Sbsh * 3848914f07Sbsh * MCIMX51 Multimedia Applications Processor 3948914f07Sbsh * Reference Manual 4048914f07Sbsh * MCIMX51RM 4148914f07Sbsh * Rev. 1 4248914f07Sbsh * 2/2010 43*a4103ccdSryo * 44*a4103ccdSryo * i.MX 6Dual/6Quad Applications Processor 45*a4103ccdSryo * Reference Manual 46*a4103ccdSryo * IMX6DQRM 47*a4103ccdSryo * Rev. 1 48*a4103ccdSryo * 4/2013 4948914f07Sbsh */ 5048914f07Sbsh 5147143f5cShkenken #ifndef _ARM_IMX_IMXWDOGREG_H 5247143f5cShkenken #define _ARM_IMX_IMXWDOGREG_H 5348914f07Sbsh 5448914f07Sbsh #define IMX_WDOG_WCR 0x0000 /* Watchdog Control Register */ 5548914f07Sbsh #define WCR_WDZST __BIT(0) /* watchdog low power */ 5648914f07Sbsh #define WCR_WDBG __BIT(1) /* watchdog debug enable */ 5748914f07Sbsh #define WCR_WDE __BIT(2) /* watchdog enable */ 5848914f07Sbsh #define WCR_WDT __BIT(3) /* timeout assertion */ 5948914f07Sbsh #define WCR_SRS __BIT(4) /* software reset signal */ 6048914f07Sbsh #define WCR_WDA __BIT(5) /* ipp_wdog* assertion */ 6148914f07Sbsh #define WCR_WDW __BIT(7) /* disable for wait */ 6247143f5cShkenken #define WCR_WT __BITS(15, 8) 6348914f07Sbsh /* watchdog timeout 6448914f07Sbsh 0=0.5sec 0xff=128sec */ 6548914f07Sbsh 6648914f07Sbsh #define IMX_WDOG_WSR 0x0002 /* Watchdog Service Register */ 6748914f07Sbsh #define WSR_MAGIC1 0x5555 /* 1st word of service sequence */ 6848914f07Sbsh #define WSR_MAGIC2 0xaaaa /* 2nd word of service sequence */ 6948914f07Sbsh 7048914f07Sbsh #define IMX_WDOG_WRSR 0x0004 /* Watchdog Reset Status Register */ 7148914f07Sbsh #define WRSR_SFTW __BIT(0) /* reset is the result of a 7248914f07Sbsh * software reset */ 7348914f07Sbsh #define WRSR_TOUT __BIT(1) /* reset is the result of a 7448914f07Sbsh * WDOG timeout */ 7548914f07Sbsh /* only for i.MX31 */ 7648914f07Sbsh #define WRSR_CMON __BIT(2) 7748914f07Sbsh #define WRSR_EXT __BIT(3) 7848914f07Sbsh #define WRSR_JRST __BIT(5) 79*a4103ccdSryo /* i.MX31 and iMX6 */ 80*a4103ccdSryo #define WRSR_PWR __BIT(4) 8148914f07Sbsh 82*a4103ccdSryo /* only for i.MX51 and i.MX6 */ 8348914f07Sbsh #define IMX_WDOG_WICR 0x0006 /* Watchdog Interrupt Control Register */ 8447143f5cShkenken #define WICR_WICT __BITS(7,0) /* interrupt count timeout */ 8548914f07Sbsh #define WICR_WTIS __BIT(14) /* interrupt status [w1c] */ 8648914f07Sbsh #define WICR_WIE __BIT(15) /* interrupt enable */ 8748914f07Sbsh 88*a4103ccdSryo /* only for i.MX51 and i.MX6 */ 8948914f07Sbsh #define IMX_WDOG_WMCR 0x0008 9048914f07Sbsh #define WMCR_PDE __BIT(0) /* power down enable */ 9148914f07Sbsh 9247143f5cShkenken #endif /* _ARM_IMX_IMXWDOGREG_H */ 93