1*94de0730Smatt /* $Id: imx23_pinctrlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2eba5cacbSjkunz 3eba5cacbSjkunz /* 4eba5cacbSjkunz * Copyright (c) 2012 The NetBSD Foundation, Inc. 5eba5cacbSjkunz * All rights reserved. 6eba5cacbSjkunz * 7eba5cacbSjkunz * This code is derived from software contributed to The NetBSD Foundation 8eba5cacbSjkunz * by Petri Laakso. 9eba5cacbSjkunz * 10eba5cacbSjkunz * Redistribution and use in source and binary forms, with or without 11eba5cacbSjkunz * modification, are permitted provided that the following conditions 12eba5cacbSjkunz * are met: 13eba5cacbSjkunz * 1. Redistributions of source code must retain the above copyright 14eba5cacbSjkunz * notice, this list of conditions and the following disclaimer. 15eba5cacbSjkunz * 2. Redistributions in binary form must reproduce the above copyright 16eba5cacbSjkunz * notice, this list of conditions and the following disclaimer in the 17eba5cacbSjkunz * documentation and/or other materials provided with the distribution. 18eba5cacbSjkunz * 19eba5cacbSjkunz * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20eba5cacbSjkunz * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21eba5cacbSjkunz * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22eba5cacbSjkunz * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23eba5cacbSjkunz * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24eba5cacbSjkunz * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25eba5cacbSjkunz * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26eba5cacbSjkunz * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27eba5cacbSjkunz * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28eba5cacbSjkunz * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29eba5cacbSjkunz * POSSIBILITY OF SUCH DAMAGE. 30eba5cacbSjkunz */ 31eba5cacbSjkunz 32eba5cacbSjkunz #ifndef _ARM_IMX_IMX23_PINCTRLREG_H_ 33eba5cacbSjkunz #define _ARM_IMX_IMX23_PINCTRLREG_H_ 34eba5cacbSjkunz 35eba5cacbSjkunz #include <sys/cdefs.h> 36eba5cacbSjkunz 37eba5cacbSjkunz #define HW_PINCTRL_BASE 0x80018000 38*94de0730Smatt #define HW_PINCTRL_SIZE 0x2000 39eba5cacbSjkunz 40eba5cacbSjkunz /* 41eba5cacbSjkunz * PINCTRL Block Control Register. 42eba5cacbSjkunz */ 43eba5cacbSjkunz #define HW_PINCTRL_CTRL 0x000 44eba5cacbSjkunz #define HW_PINCTRL_CTRL_SET 0x004 45eba5cacbSjkunz #define HW_PINCTRL_CTRL_CLR 0x008 46eba5cacbSjkunz #define HW_PINCTRL_CTRL_TOG 0x00C 47eba5cacbSjkunz 48eba5cacbSjkunz #define HW_PINCTRL_CTRL_SFTRST __BIT(31) 49eba5cacbSjkunz #define HW_PINCTRL_CTRL_CLKGATE __BIT(30) 50eba5cacbSjkunz #define HW_PINCTRL_CTRL_RSRVD2 __BITS(29, 28) 51eba5cacbSjkunz #define HW_PINCTRL_CTRL_PRESENT3 __BIT(27) 52eba5cacbSjkunz #define HW_PINCTRL_CTRL_PRESENT2 __BIT(26) 53eba5cacbSjkunz #define HW_PINCTRL_CTRL_PRESENT1 __BIT(25) 54eba5cacbSjkunz #define HW_PINCTRL_CTRL_PRESENT0 __BIT(24) 55eba5cacbSjkunz #define HW_PINCTRL_CTRL_RSRVD1 __BIT(23, 3) 56eba5cacbSjkunz #define HW_PINCTRL_CTRL_IRQOUT2 __BITS(2) 57eba5cacbSjkunz #define HW_PINCTRL_CTRL_IRQOUT1 __BIT(1) 58eba5cacbSjkunz #define HW_PINCTRL_CTRL_IRQOUT0 __BIT(0) 59eba5cacbSjkunz 60eba5cacbSjkunz /* 61eba5cacbSjkunz * PINCTRL Pin Mux Select Register 0. 62eba5cacbSjkunz */ 63eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0 0x100 64eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_SET 0x104 65eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_CLR 0x108 66eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_TOG 0x10C 67eba5cacbSjkunz 68eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15 __BITS(31, 30) 69eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14 __BITS(29, 28) 70eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13 __BITS(27, 26) 71eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12 __BITS(25, 24) 72eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11 __BITS(23, 22) 73eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10 __BITS(21, 20) 74eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09 __BITS(19, 18) 75eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08 __BITS(17, 16) 76eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07 __BITS(15, 14) 77eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06 __BITS(13, 12) 78eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05 __BITS(11, 10) 79eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04 __BITS(9, 8) 80eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03 __BITS(7, 6) 81eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02 __BITS(5, 4) 82eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01 __BITS(3, 2) 83eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00 __BITS(1, 0) 84eba5cacbSjkunz 85eba5cacbSjkunz /* Pin 59, GPMI_D15 pin function selection */ 86eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_DATA15 0x00 87eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_AUART2_TX 0x01 88eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_CE3N 0x02 89eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPIO 0x03 90eba5cacbSjkunz 91eba5cacbSjkunz /* Pin 58, GPMI_D14 pin function selection */ 92eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPMI_DATA14 0x00 93eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_AUART2_RX 0x01 94eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_RESERVED 0x02 95eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPIO 0x03 96eba5cacbSjkunz 97eba5cacbSjkunz /* Pin 57, GPMI_D13 pin function selection */ 98eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPMI_DATA13 0x00 99eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_LCD_D23 0x01 100eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_RESERVED 0x02 101eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPIO 0x03 102eba5cacbSjkunz 103eba5cacbSjkunz /* Pin 56, GPMI_D12 pin function selection */ 104eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPMI_DATA12 0x00 105eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_LCD_D22 0x01 106eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_RESERVED 0x02 107eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPIO 0x03 108eba5cacbSjkunz 109eba5cacbSjkunz /* Pin 55, GPMI_D11 pin function selection */ 110eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPMI_DATA11 0x00 111eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_LCD_D21 0x01 112eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_SSP1_D7 0x02 113eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPIO 0x03 114eba5cacbSjkunz 115eba5cacbSjkunz /* Pin 54, GPMI_D10 pin function selection */ 116eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPMI_DATA10 0x00 117eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_LCD_D20 0x01 118eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_SSP1_D6 0x02 119eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPIO 0x03 120eba5cacbSjkunz 121eba5cacbSjkunz /* Pin 53, GPMI_D09 pin function selection */ 122eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPMI_DATA09 0x00 123eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_LCD_D19 0x01 124eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_SSP1_D5 0x02 125eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPIO 0x03 126eba5cacbSjkunz 127eba5cacbSjkunz /* Pin 52, GPMI_D08 pin function selection */ 128eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPMI_DATA08 0x00 129eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_LCD_D18 0x01 130eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_SSP1_D4 0x02 131eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPIO 0x03 132eba5cacbSjkunz 133eba5cacbSjkunz /* Pin 50, GPMI_D07 pin function selection */ 134eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPMI_DATA07 0x00 135eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_LCD_D15 0x01 136eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_SSP2_D7 0x02 137eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPIO 0x03 138eba5cacbSjkunz 139eba5cacbSjkunz /* Pin 51, GPMI_D06 pin function selection */ 140eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPMI_DATA06 0x00 141eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_LCD_D14 0x01 142eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_SSP2_D6 0x02 143eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPIO 0x03 144eba5cacbSjkunz 145eba5cacbSjkunz /* Pin 48, GPMI_D05 pin function selection */ 146eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPMI_DATA05 0x00 147eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_LCD_D13 0x01 148eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_SSP2_D5 0x02 149eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPIO 0x03 150eba5cacbSjkunz 151eba5cacbSjkunz /* Pin 49, GPMI_D04 pin function selection */ 152eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPMI_DATA04 0x00 153eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_LCD_D12 0x01 154eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_SSP2_D4 0x02 155eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPIO 0x03 156eba5cacbSjkunz 157eba5cacbSjkunz /* Pin 47, GPMI_D03 pin function selection */ 158eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPMI_DATA03 0x00 159eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_LCD_D11 0x01 160eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_SSP2_D3 0x02 161eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPIO 0x03 162eba5cacbSjkunz 163eba5cacbSjkunz /* Pin 46, GPMI_D02 pin function selection */ 164eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPMI_DATA02 0x00 165eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_LCD_D10 0x01 166eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_SSP2_D2 0x02 167eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPIO 0x03 168eba5cacbSjkunz 169eba5cacbSjkunz /* Pin 45, GPMI_D01 pin function selection */ 170eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPMI_DATA01 0x00 171eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_LCD_D9 0x01 172eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_SSP2_D1 0x02 173eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPIO 0x03 174eba5cacbSjkunz 175eba5cacbSjkunz /* Pin 44, GPMI_D00 pin function selection */ 176eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPMI_DATA00 0x00 177eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_LCD_D8 0x01 178eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_SSP2_D0 0x02 179eba5cacbSjkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPIO 0x03 180eba5cacbSjkunz 181eba5cacbSjkunz /* 182eba5cacbSjkunz * PINCTRL Pin Mux Select Register 1. 183eba5cacbSjkunz */ 184eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1 0x110 185eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_SET 0x114 186eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_CLR 0x118 187eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_TOG 0x11C 188eba5cacbSjkunz 189eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31 __BITS(31, 30) 190eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30 __BITS(29, 28) 191eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29 __BITS(27, 26) 192eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28 __BITS(25, 24) 193eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27 __BITS(23, 22) 194eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26 __BITS(21, 20) 195eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25 __BITS(19, 18) 196eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24 __BITS(17, 16) 197eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23 __BITS(15, 14) 198eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22 __BITS(13, 12) 199eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21 __BITS(11, 10) 200eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20 __BITS(9, 8) 201eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19 __BITS(7, 6) 202eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18 __BITS(5, 4) 203eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17 __BITS(3, 2) 204eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16 __BITS(1, 0) 205eba5cacbSjkunz 206eba5cacbSjkunz /* Pin 4, I2C_SDA pin function selection */ 207eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_I2C_SD 0x00 208eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPMI_CE2N 0x01 209eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_AUART1_RX 0x02 210eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPIO 0x03 211eba5cacbSjkunz 212eba5cacbSjkunz /* Pin 2, I2C_SCL pin function selection */ 213eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_I2C_CLK 0x00 214eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPMI_READY2 0x01 215eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_AUART1_TX 0x02 216eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPIO 0x03 217eba5cacbSjkunz 218eba5cacbSjkunz /* Pin 69, AUART1_TX pin function selection */ 219eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_AUART1_TX 0x00 220eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_RESERVED 0x01 221eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_SSP1_D7 0x02 222eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_GPIO 0x03 223eba5cacbSjkunz 224eba5cacbSjkunz /* Pin 68, AUART1_RX pin function selection */ 225eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_AUART1_RX 0x00 226eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_RESERVED 0x01 227eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_SSP1_D6 0x02 228eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_GPIO 0x03 229eba5cacbSjkunz 230eba5cacbSjkunz /* Pin 67, AUART1_RTS pin function selection */ 231eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_AUART1_RTS 0x00 232eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_RESERVED 0x01 233eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_SSP1_D5 0x02 234eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_GPIO 0x03 235eba5cacbSjkunz 236eba5cacbSjkunz /* Pin 66, AUART1_CTS pin function selection */ 237eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_AUART1_CTS 0x00 238eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_ESERVED 0x01 239eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_SSP1_D4 0x02 240eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_GPIO 0x03 241eba5cacbSjkunz 242eba5cacbSjkunz /* Pin 60, GPMI_RDN pin function selection */ 243eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPMI_RDN 0x00 244eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED1 0x01 245eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED2 0x02 246eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPIO 0x03 247eba5cacbSjkunz 248eba5cacbSjkunz /* Pin 65, GPMI_WRN pin function selection */ 249eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPMI_WRN 0x00 250eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_RESERVED 0x01 251eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_SSP2_SCK 0x02 252eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPIO 0x03 253eba5cacbSjkunz 254eba5cacbSjkunz /* Pin 64, GPMI_WPN pin function selection */ 255eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPMI_WPN 0x00 256eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED1 0x01 257eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED2 0x02 258eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPIO 0x03 259eba5cacbSjkunz 260eba5cacbSjkunz /* Pin 63, GPMI_RDY3 pin function selection */ 261eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPMI_READY3 0x00 262eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED1 0x01 263eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED2 0x02 264eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPIO 0x03 265eba5cacbSjkunz 266eba5cacbSjkunz /* Pin 62, GPMI_RDY2 pin function selection */ 267eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPMI_READY2 0x00 268eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED1 0x01 269eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED2 0x02 270eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPIO 0x03 271eba5cacbSjkunz 272eba5cacbSjkunz /* Pin 43, GPMI_RDY1 pin function selection */ 273eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPMI_READY1 0x00 274eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_RESERVED 0x01 275eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_SSP2_CMD 0x02 276eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPIO 0x03 277eba5cacbSjkunz 278eba5cacbSjkunz /* Pin 61, GPMI_RDY0 pin function selection */ 279eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPMI_READY0 0x00 280eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_RESERVED 0x01 281eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_SSP2_DETECT 0x02 282eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPIO 0x03 283eba5cacbSjkunz 284eba5cacbSjkunz /* Pin 42, GPMI_CE2N pin function selection */ 285eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPMI_CE2N 0x00 286eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED1 0x01 287eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED2 0x02 288eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPIO 0x03 289eba5cacbSjkunz 290eba5cacbSjkunz /* Pin 41, GPMI_ALE pin function selection */ 291eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPMI_ALE 0x00 292eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_LCD_D17 0x01 293eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_RESERVED 0x02 294eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPIO 0x03 295eba5cacbSjkunz 296eba5cacbSjkunz /* Pin 40, GPMI_CLE pin function selection */ 297eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPMI_CLE 0x00 298eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_LCD_D16 0x01 299eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_RESERVED 0x02 300eba5cacbSjkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPIO 0x03 301eba5cacbSjkunz 302eba5cacbSjkunz /* 303eba5cacbSjkunz * PINCTRL Pin Mux Select Register 2. 304eba5cacbSjkunz */ 305eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2 0x120 306eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_SET 0x124 307eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_CLR 0x128 308eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_TOG 0x12C 309eba5cacbSjkunz 310eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15 __BITS(31, 30) 311eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14 __BITS(29, 28) 312eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13 __BITS(27, 26) 313eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12 __BITS(25, 24) 314eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11 __BITS(23, 22) 315eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10 __BITS(21, 20) 316eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09 __BITS(19, 18) 317eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08 __BITS(17, 16) 318eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07 __BITS(15, 14) 319eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06 __BITS(13, 12) 320eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05 __BITS(11, 10) 321eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04 __BITS(9, 8) 322eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03 __BITS(7, 6) 323eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02 __BITS(5, 4) 324eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01 __BITS(3, 2) 325eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00 __BITS(1, 0) 326eba5cacbSjkunz 327eba5cacbSjkunz /* Pin 15, LCD_D15 pin function selection */ 328eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_LCD_D15 0x00 329eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_ETM_DA7 0x01 330eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_SAIF1_SDATA1 0x02 331eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_GPIO 0x03 332eba5cacbSjkunz 333eba5cacbSjkunz /* Pin 17, LCD_D14 pin function selection */ 334eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_LCD_D14 0x00 335eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_ETM_DA6 0x01 336eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_SAIF1_SDATA2 0x02 337eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_GPIO 0x03 338eba5cacbSjkunz 339eba5cacbSjkunz /* Pin 19, LCD_D13 pin function selection */ 340eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_LCD_D13 0x00 341eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_ETM_DA5 0x01 342eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_SAIF2_SDATA2 0x02 343eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_GPIO 0x03 344eba5cacbSjkunz 345eba5cacbSjkunz /* Pin 22, LCD_D12 pin function selection */ 346eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_LCD_D12 0x00 347eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_ETM_DA4 0x01 348eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_SAIF2_SDATA1 0x02 349eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_GPIO 0x03 350eba5cacbSjkunz 351eba5cacbSjkunz /* Pin 24, LCD_D11 pin function selection */ 352eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_LCD_D11 0x00 353eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_ETM_DA3 0x01 354eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_SAIF_LRCLK 0x02 355eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_GPIO 0x03 356eba5cacbSjkunz 357eba5cacbSjkunz /* Pin 26, LCD_D10 pin function selection */ 358eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_LCD_D10 0x00 359eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_ETM_DA2 0x01 360eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_SAIF_BITCLK 0x02 361eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_GPIO 0x03 362eba5cacbSjkunz 363eba5cacbSjkunz /* Pin 28, LCD_D09 pin function selection */ 364eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_LCD_D9 0x00 365eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_ETM_DA1 0x01 366eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_SAIF1_SDATA0 0x02 367eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_GPIO 0x03 368eba5cacbSjkunz 369eba5cacbSjkunz /* Pin 27, LCD_D08 pin function selection */ 370eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_LCD_D8 0x00 371eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_ETM_DA0 0x01 372eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_SAIF2_SDATA0 0x02 373eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_GPIO 0x03 374eba5cacbSjkunz 375eba5cacbSjkunz /* Pin 25, LCD_D07 pin function selection */ 376eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_LCD_D7 0x00 377eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_ETM_DA15 0x01 378eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_RESERVED 0x02 379eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_GPIO 0x03 380eba5cacbSjkunz 381eba5cacbSjkunz /* Pin 23, LCD_D06 pin function selection */ 382eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_LCD_D6 0x00 383eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_ETM_DA14 0x01 384eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_RESERVED 0x02 385eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_GPIO 0x03 386eba5cacbSjkunz 387eba5cacbSjkunz /* Pin 21, LCD_D05 pin function selection */ 388eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_LCD_D5 0x00 389eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_ETM_DA13 0x01 390eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_RESERVED 0x02 391eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_GPIO 0x03 392eba5cacbSjkunz 393eba5cacbSjkunz /* Pin 18, LCD_D04 pin function selection */ 394eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_LCD_D4 0x00 395eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_ETM_DA12 0x01 396eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_RESERVED 0x02 397eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_GPIO 0x03 398eba5cacbSjkunz 399eba5cacbSjkunz /* Pin 16, LCD_D03 pin function selection */ 400eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_LCD_D3 0x00 401eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_ETM_DA11 0x01 402eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_RESERVED 0x02 403eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_GPIO 0x03 404eba5cacbSjkunz 405eba5cacbSjkunz /* Pin 14, LCD_D02 pin function selection */ 406eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_LCD_D2 0x00 407eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_ETM_DA10 0x01 408eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_RESERVED 0x02 409eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_GPIO 0x03 410eba5cacbSjkunz 411eba5cacbSjkunz /* Pin 12, LCD_D01 pin function selection */ 412eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_LCD_D1 0x00 413eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_ETM_DA9 0x01 414eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_RESERVED 0x02 415eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_GPIO 0x03 416eba5cacbSjkunz 417eba5cacbSjkunz /* Pin 10, LCD_D00 pin function selection */ 418eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_LCD_D0 0x00 419eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_ETM_DA8 0x01 420eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_RESERVED 0x02 421eba5cacbSjkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_GPIO 0x03 422eba5cacbSjkunz 423eba5cacbSjkunz /* 424eba5cacbSjkunz * PINCTRL Pin Mux Select Register 3. 425eba5cacbSjkunz */ 426eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3 0x130 427eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_SET 0x134 428eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_CLR 0x138 429eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_TOG 0x13C 430eba5cacbSjkunz 431eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_RSRVD0 __BITS(31, 30) 432eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30 __BITS(29, 28) 433eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29 __BITS(27, 26) 434eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28 __BITS(25, 24) 435eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27 __BITS(23, 22) 436eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26 __BITS(21, 20) 437eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25 __BITS(19, 18) 438eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24 __BITS(17, 16) 439eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23 __BITS(15, 14) 440eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22 __BITS(13, 12) 441eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21 __BITS(11, 10) 442eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20 __BITS(9, 8) 443eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19 __BITS(7, 6) 444eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18 __BITS(5, 4) 445eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17 __BITS(3, 2) 446eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16 __BITS(1, 0) 447eba5cacbSjkunz 448eba5cacbSjkunz /* Always write zeroes to this field */ 449eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_RSRVD0_ZERO 0x00 450eba5cacbSjkunz 451eba5cacbSjkunz /* Pin 131, PWM4 pin function selection */ 452eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_PWM4 0x00 453eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_ETM_TCLK 0x01 454eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_AUART1_RTS 0x02 455eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_GPIO 0x03 456eba5cacbSjkunz 457eba5cacbSjkunz /* Pin 130, PWM3 pin function selection */ 458eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_PWM3 0x00 459eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_ETM_TCTL 0x01 460eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_AUART1_CTS 0x02 461eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_GPIO 0x03 462eba5cacbSjkunz 463eba5cacbSjkunz /* Pin 129, PWM2 pin function selection */ 464eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_PWM2 0x00 465eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPMI_READY3 0x01 466eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_RESERVED 0x02 467eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPIO 0x03 468eba5cacbSjkunz 469eba5cacbSjkunz /* Pin 3, PWM1 pin function selection */ 470eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_PWM1 0x00 471eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_TIMROT2 0x01 472eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_DUART_TX 0x02 473eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_GPIO 0x03 474eba5cacbSjkunz 475eba5cacbSjkunz /* Pin 1, PWM0 pin function selection */ 476eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_PWM0 0x00 477eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_TIMROT1 0x01 478eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_DUART_RX 0x02 479eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_GPIO 0x03 480eba5cacbSjkunz 481eba5cacbSjkunz /* Pin 35, LCD_VSYNC pin function selection */ 482eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_VSYNC 0x00 483eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_BUSY 0x01 484eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_RESERVED 0x02 485eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_GPIO 0x03 486eba5cacbSjkunz 487eba5cacbSjkunz /* Pin 34, LCD_HSYNC pin function selection */ 488eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_LCD_HSYNC 0x00 489eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_I2C_SD 0x01 490eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_RESERVED 0x02 491eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_GPIO 0x03 492eba5cacbSjkunz 493eba5cacbSjkunz /* Pin 30, LCD_ENABLE pin function selection */ 494eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_LCD_ENABLE 0x00 495eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_I2C_CLK 0x01 496eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_RESERVED 0x02 497eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_GPIO 0x03 498eba5cacbSjkunz 499eba5cacbSjkunz /* Pin 36, LCD_DOTCK pin function selection */ 500eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_LCD_DOTCK 0x00 501eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPMI_READY3 0x01 502eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_RESERVED 0x02 503eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPIO 0x03 504eba5cacbSjkunz 505eba5cacbSjkunz /* Pin 29, LCD_CS pin function selection */ 506eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_LCD_CS 0x00 507eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED1 0x01 508eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED2 0x02 509eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_GPIO 0x03 510eba5cacbSjkunz 511eba5cacbSjkunz /* Pin 32, LCD_WR pin function selection */ 512eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_LCD_WR 0x00 513eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED1 0x01 514eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED2 0x02 515eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_GPIO 0x03 516eba5cacbSjkunz 517eba5cacbSjkunz /* Pin 33, LCD_RS pin function selection */ 518eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_LCD_RS 0x00 519eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_ETM_TCLK 0x01 520eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_RESERVED 0x02 521eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_GPIO 0x03 522eba5cacbSjkunz 523eba5cacbSjkunz /* Pin 31, LCD_RESET pin function selection */ 524eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_LCD_RESET 0x00 525eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_ETM_TCTL 0x01 526eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPMI_CE3N 0x02 527eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPIO 0x03 528eba5cacbSjkunz 529eba5cacbSjkunz /* Pin 11, LCD_D17 pin function selection */ 530eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_LCD_D17 0x00 531eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED1 0x01 532eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED2 0x02 533eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_GPIO 0x03 534eba5cacbSjkunz 535eba5cacbSjkunz /* Pin 13, LCD_D16 pin function selection */ 536eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_LCD_D16 0x00 537eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_RESERVED 0x01 538eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_SAIF_ALT_BITCLK 0x02 539eba5cacbSjkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_GPIO 0x03 540eba5cacbSjkunz 541eba5cacbSjkunz /* 542eba5cacbSjkunz * PINCTRL Pin Mux Select Register 4. 543eba5cacbSjkunz */ 544eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4 0x140 545eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_SET 0x144 546eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_CLR 0x148 547eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_TOG 0x14C 548eba5cacbSjkunz 549eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15 __BITS(31,30) 550eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14 __BITS(29,28) 551eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13 __BITS(27,26) 552eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12 __BITS(25,24) 553eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11 __BITS(23,22) 554eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10 __BITS(21,20) 555eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09 __BITS(19,18) 556eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08 __BITS(17,16) 557eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07 __BITS(15,14) 558eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06 __BITS(13,12) 559eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05 __BITS(11,10) 560eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04 __BITS(9,8) 561eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03 __BITS(7,6) 562eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02 __BITS(5,4) 563eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01 __BITS(3,2) 564eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00 __BITS(1,0) 565eba5cacbSjkunz 566eba5cacbSjkunz /* Pin 108, EMI_A06 pin function selection */ 567eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_EMI_ADDR06 0x00 568eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED1 0x01 569eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED2 0x02 570eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_GPIO 0x03 571eba5cacbSjkunz 572eba5cacbSjkunz /* Pin 107, EMI_A05 pin function selection */ 573eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_EMI_ADDR05 0x00 574eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED1 0x01 575eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED2 0x02 576eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_GPIO 0x03 577eba5cacbSjkunz 578eba5cacbSjkunz /* Pin 109, EMI_A04 pin function selection */ 579eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_EMI_ADDR04 0x00 580eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED1 0x01 581eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED2 0x02 582eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_GPIO 0x03 583eba5cacbSjkunz 584eba5cacbSjkunz /* Pin 110, EMI_A03 pin function selection */ 585eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_EMI_ADDR03 0x00 586eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED1 0x01 587eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED2 0x02 588eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_GPIO 0x03 589eba5cacbSjkunz 590eba5cacbSjkunz /* Pin 111, EMI_A02 pin function selection */ 591eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_EMI_ADDR02 0x00 592eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED1 0x01 593eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED2 0x02 594eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_GPIO 0x03 595eba5cacbSjkunz 596eba5cacbSjkunz /* Pin 112, EMI_A01 pin function selection */ 597eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_EMI_ADDR01 0x00 598eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED1 0x01 599eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED2 0x02 600eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_GPIO 0x03 601eba5cacbSjkunz 602eba5cacbSjkunz /* Pin 113, EMI_A00 pin function selection */ 603eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_EMI_ADDR00 0x00 604eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED1 0x01 605eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED2 0x02 606eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_GPIO 0x03 607eba5cacbSjkunz 608eba5cacbSjkunz /* Pin 38, ROTARYB pin function selection */ 609eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_TIMROT2 0x00 610eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_AUART2_CTS 0x01 611eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPMI_CE3N 0x02 612eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPIO 0x03 613eba5cacbSjkunz 614eba5cacbSjkunz /* Pin 37, ROTARYA pin function selection */ 615eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_TIMROT1 0x00 616eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_AUART2_RTS 0x01 617eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_SPDIF 0x02 618eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_GPIO 0x03 619eba5cacbSjkunz 620eba5cacbSjkunz /* Pin 127, SSP1_SCK pin function selection */ 621eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_SSP1_SCK 0x00 622eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_RESERVED 0x01 623eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_ALT_JTAG_TRST_N 0x02 624eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_GPIO 0x03 625eba5cacbSjkunz 626eba5cacbSjkunz /* Pin 125, SSP1_DATA3 pin function selection */ 627eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_SSP1_D3 0x00 628eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_RESERVED 0x01 629eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_ALT_JTAG_TMS 0x02 630eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_GPIO 0x03 631eba5cacbSjkunz 632eba5cacbSjkunz /* Pin 124, SSP1_DATA2 pin function selection */ 633eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_SSP1_D2 0x00 634eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_I2C_SD 0x01 635eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_ALT_JTAG_RTCK 0x02 636eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_GPIO 0x03 637eba5cacbSjkunz 638eba5cacbSjkunz /* Pin 123, SSP1_DATA1 pin function selection */ 639eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_SSP1_D1 0x00 640eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_I2C_CLK 0x01 641eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_ALT_JTAG_TCK 0x02 642eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_GPIO 0x03 643eba5cacbSjkunz 644eba5cacbSjkunz /* Pin 122, SSP1_DATA0 pin function selection */ 645eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_SSP1_D0 0x00 646eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_RESERVED 0x01 647eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_ALT_JTAG_TDI 0x02 648eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_GPIO 0x03 649eba5cacbSjkunz 650eba5cacbSjkunz /* Pin 126, SSP1_DETECT pin function selection */ 651eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_SSP1_DETECT 0x00 652eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPMI_CE3N 0x01 653eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_USB_ID 0x02 654eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPIO 0x03 655eba5cacbSjkunz 656eba5cacbSjkunz /* Pin 121, SSP1_CMD pin function selection */ 657eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_SSP1_CMD 0x00 658eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_RESERVED 0x01 659eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_ALT_JTAG_TDO 0x02 660eba5cacbSjkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_GPIO 0x03 661eba5cacbSjkunz 662eba5cacbSjkunz /* 663eba5cacbSjkunz * PINCTRL Pin Mux Select Register 5. 664eba5cacbSjkunz */ 665eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5 0x150 666eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_SET 0x154 667eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_CLR 0x158 668eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_TOG 0x15C 669eba5cacbSjkunz 670eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31 __BITS(31,30) 671eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30 __BITS(29,28) 672eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29 __BITS(27,26) 673eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28 __BITS(25,24) 674eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27 __BITS(23,22) 675eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26 __BITS(21,20) 676eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25 __BITS(19,18) 677eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24 __BITS(17,16) 678eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23 __BITS(15,14) 679eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22 __BITS(13,12) 680eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21 __BITS(11,10) 681eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20 __BITS(9,8) 682eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19 __BITS(7,6) 683eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18 __BITS(5,4) 684eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17 __BITS(3,2) 685eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16 __BITS(1,0) 686eba5cacbSjkunz 687eba5cacbSjkunz /* Pin 114, EMI_WEN pin function selection */ 688eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_EMI_WEN 0x00 689eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED1 0x01 690eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED2 0x02 691eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_GPIO 0x03 692eba5cacbSjkunz 693eba5cacbSjkunz /* Pin 98, EMI_RASN pin function selection */ 694eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_EMI_RASN 0x00 695eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED1 0x01 696eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED2 0x02 697eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_GPIO 0x03 698eba5cacbSjkunz 699eba5cacbSjkunz /* Pin 115, EMI_CKE pin function selection */ 700eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_EMI_CKE 0x00 701eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED1 0x01 702eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED2 0x02 703eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_GPIO 0x03 704eba5cacbSjkunz 705eba5cacbSjkunz /* Pin 120, GPMI_CE0N pin function selection */ 706eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPMI_CE0N 0x00 707eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED1 0x01 708eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED2 0x02 709eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPIO 0x03 710eba5cacbSjkunz 711eba5cacbSjkunz /* Pin 118, GPMI_CE1N pin function selection */ 712eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPMI_CE1N 0x00 713eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED1 0x01 714eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED2 0x02 715eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPIO 0x03 716eba5cacbSjkunz 717eba5cacbSjkunz /* Pin 99, EMI_CE1N pin function selection */ 718eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_EMI_CE1N 0x00 719eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED1 0x01 720eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED2 0x02 721eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_GPIO 0x03 722eba5cacbSjkunz 723eba5cacbSjkunz /* Pin 100, EMI_CE0N pin function selection */ 724eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_EMI_CE0N 0x00 725eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED1 0x01 726eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED2 0x02 727eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_GPIO 0x03 728eba5cacbSjkunz 729eba5cacbSjkunz /* Pin 97, EMI_CASN pin function selection */ 730eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_EMI_CASN 0x00 731eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED1 0x01 732eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED2 0x02 733eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_GPIO 0x03 734eba5cacbSjkunz 735eba5cacbSjkunz /* Pin 117, EMI_BA1 pin function selection */ 736eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_EMI_BA1 0x00 737eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED1 0x01 738eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED2 0x02 739eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_GPIO 0x03 740eba5cacbSjkunz 741eba5cacbSjkunz /* Pin 116, EMI_BA0 pin function selection */ 742eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_EMI_BA0 0x00 743eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED1 0x01 744eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED2 0x02 745eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_GPIO 0x03 746eba5cacbSjkunz 747eba5cacbSjkunz /* Pin 101, EMI_A12 pin function selection */ 748eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_EMI_ADDR12 0x00 749eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED1 0x01 750eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED2 0x02 751eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_GPIO 0x03 752eba5cacbSjkunz 753eba5cacbSjkunz /* Pin 102, EMI_A11 pin function selection */ 754eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_EMI_ADDR11 0x00 755eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED1 0x01 756eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED2 0x02 757eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_GPIO 0x03 758eba5cacbSjkunz 759eba5cacbSjkunz /* Pin 104, EMI_A10 pin function selection */ 760eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_EMI_ADDR10 0x00 761eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED1 0x01 762eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED2 0x02 763eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_GPIO 0x03 764eba5cacbSjkunz 765eba5cacbSjkunz /* Pin 103, EMI_A09 pin function selection */ 766eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_EMI_ADDR09 0x00 767eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED1 0x01 768eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED2 0x02 769eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_GPIO 0x03 770eba5cacbSjkunz 771eba5cacbSjkunz /* Pin 106, EMI_A08 pin function selection */ 772eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_EMI_ADDR08 0x00 773eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED1 0x01 774eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED2 0x02 775eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_GPIO 0x03 776eba5cacbSjkunz 777eba5cacbSjkunz /* Pin 105, EMI_A07 pin function selection */ 778eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_EMI_ADDR07 0x00 779eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED1 0x01 780eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED2 0x02 781eba5cacbSjkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_GPIO 0x03 782eba5cacbSjkunz 783eba5cacbSjkunz /* 784eba5cacbSjkunz * PINCTRL Pin Mux Select Register 6. 785eba5cacbSjkunz */ 786eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6 0x160 787eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_SET 0x164 788eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_CLR 0x168 789eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_TOG 0x16C 790eba5cacbSjkunz 791eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15 __BITS(31,30) 792eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14 __BITS(29,28) 793eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13 __BITS(27,26) 794eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12 __BITS(25,24) 795eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11 __BITS(23,22) 796eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10 __BITS(21,20) 797eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09 __BITS(19,18) 798eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08 __BITS(17,16) 799eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07 __BITS(15,14) 800eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06 __BITS(13,12) 801eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05 __BITS(11,10) 802eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04 __BITS(9,8) 803eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03 __BITS(7,6) 804eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02 __BITS(5,4) 805eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01 __BITS(3,2) 806eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00 __BITS(1,0) 807eba5cacbSjkunz 808eba5cacbSjkunz /* Pin 95, EMI_D15 pin function selection */ 809eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_EMI_DATA15 0x00 810eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED1 0x01 811eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED2 0x02 812eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_DISABLED 0x03 813eba5cacbSjkunz 814eba5cacbSjkunz /* Pin 96, EMI_D14 pin function selection */ 815eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_EMI_DATA14 0x00 816eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED1 0x01 817eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED2 0x02 818eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_DISABLED 0x03 819eba5cacbSjkunz 820eba5cacbSjkunz /* Pin 94, EMI_D13 pin function selection */ 821eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_EMI_DATA13 0x00 822eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED1 0x01 823eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED2 0x02 824eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_DISABLED 0x03 825eba5cacbSjkunz 826eba5cacbSjkunz /* Pin 93, EMI_D12 pin function selection */ 827eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_EMI_DATA12 0x00 828eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED1 0x01 829eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED2 0x02 830eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_DISABLED 0x03 831eba5cacbSjkunz 832eba5cacbSjkunz /* Pin 91, EMI_D11 pin function selection */ 833eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_EMI_DATA11 0x00 834eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED1 0x01 835eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED2 0x02 836eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_DISABLED 0x03 837eba5cacbSjkunz 838eba5cacbSjkunz /* Pin 89, EMI_D10 pin function selection */ 839eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_EMI_DATA10 0x00 840eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED1 0x01 841eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED2 0x02 842eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_DISABLED 0x03 843eba5cacbSjkunz 844eba5cacbSjkunz /* Pin 87, EMI_D09 pin function selection */ 845eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_EMI_DATA09 0x00 846eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED1 0x01 847eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED2 0x02 848eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_DISABLED 0x03 849eba5cacbSjkunz 850eba5cacbSjkunz /* Pin 86, EMI_D08 pin function selection */ 851eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_EMI_DATA08 0x00 852eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED1 0x01 853eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED2 0x02 854eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_DISABLED 0x03 855eba5cacbSjkunz 856eba5cacbSjkunz /* Pin 85, EMI_D07 pin function selection */ 857eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_EMI_DATA07 0x00 858eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED1 0x01 859eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED2 0x02 860eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_DISABLED 0x03 861eba5cacbSjkunz 862eba5cacbSjkunz /* Pin 84, EMI_D06 pin function selection */ 863eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_EMI_DATA06 0x00 864eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED1 0x01 865eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED2 0x02 866eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_DISABLED 0x03 867eba5cacbSjkunz 868eba5cacbSjkunz /* Pin 83, EMI_D05 pin function selection */ 869eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_EMI_DATA05 0x00 870eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED1 0x01 871eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED2 0x02 872eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_DISABLED 0x03 873eba5cacbSjkunz 874eba5cacbSjkunz /* Pin 82, EMI_D04 pin function selection */ 875eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_EMI_DATA04 0x00 876eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED1 0x01 877eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED2 0x02 878eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_DISABLED 0x03 879eba5cacbSjkunz 880eba5cacbSjkunz /* Pin 79, EMI_D03 pin function selection */ 881eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_EMI_DATA03 0x00 882eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED1 0x01 883eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED2 0x02 884eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_DISABLED 0x03 885eba5cacbSjkunz 886eba5cacbSjkunz /* Pin 77, EMI_D02 pin function selection */ 887eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_EMI_DATA02 0x00 888eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED1 0x01 889eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED2 0x02 890eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_DISABLED 0x03 891eba5cacbSjkunz 892eba5cacbSjkunz /* Pin 76, EMI_D01 pin function selection */ 893eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_EMI_DATA01 0x00 894eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED1 0x01 895eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED2 0x02 896eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_DISABLED 0x03 897eba5cacbSjkunz 898eba5cacbSjkunz /* Pin 75, EMI_D00 pin function selection */ 899eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_EMI_DATA00 0x00 900eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED1 0x01 901eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED2 0x02 902eba5cacbSjkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_DISABLED 0x03 903eba5cacbSjkunz 904eba5cacbSjkunz /* 905eba5cacbSjkunz * PINCTRL Pin Mux Select Register 7. 906eba5cacbSjkunz */ 907eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7 0x170 908eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_SET 0x174 909eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_CLR 0x178 910eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_TOG 0x17C 911eba5cacbSjkunz 912eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_RSRVD0 __BITS(31,12) 913eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21 __BITS(11,10) 914eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20 __BITS(9,8) 915eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19 __BITS(7,6) 916eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18 __BITS(5,4) 917eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17 __BITS(3,2) 918eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16 __BITS(1,0) 919eba5cacbSjkunz 920eba5cacbSjkunz /* Always write zeroes to this field */ 921eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_RSRVD0_ZERO 0x00 922eba5cacbSjkunz 923eba5cacbSjkunz /* Pin 72, EMI_CLKN pin function selection */ 924eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_EMI_CLKN 0x00 925eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED1 0x01 926eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED2 0x02 927eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_DISABLED 0x03 928eba5cacbSjkunz 929eba5cacbSjkunz /* Pin 70, EMI_CLK pin function selection */ 930eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_EMI_CLK 0x00 931eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED1 0x01 932eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED2 0x02 933eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_DISABLED 0x03 934eba5cacbSjkunz 935eba5cacbSjkunz /* Pin 74, EMI_DQS1 pin function selection */ 936eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_EMI_DQS1 0x00 937eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED1 0x01 938eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED2 0x02 939eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_DISABLED 0x03 940eba5cacbSjkunz 941eba5cacbSjkunz /* Pin 73, EMI_DQS0 pin function selection */ 942eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_EMI_DQS0 0x00 943eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED1 0x01 944eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED2 0x02 945eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_DISABLED 0x03 946eba5cacbSjkunz 947eba5cacbSjkunz /* Pin 92, EMI_DQM1 pin function selection */ 948eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_EMI_DQM1 0x00 949eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED1 0x01 950eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED2 0x02 951eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_DISABLED 0x03 952eba5cacbSjkunz 953eba5cacbSjkunz /* Pin 81, EMI_DQM0 pin function selection */ 954eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_EMI_DQM0 0x00 955eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED1 0x01 956eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED2 0x02 957eba5cacbSjkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_DISABLED 0x03 958eba5cacbSjkunz 959eba5cacbSjkunz /* 960*94de0730Smatt * PINCTRL Drive Strength and Voltage Register 0. 961*94de0730Smatt */ 962*94de0730Smatt #define HW_PINCTRL_DRIVE0 0x200 963*94de0730Smatt #define HW_PINCTRL_DRIVE0_SET 0x204 964*94de0730Smatt #define HW_PINCTRL_DRIVE0_CLR 0x208 965*94de0730Smatt #define HW_PINCTRL_DRIVE0_TOG 0x20C 966*94de0730Smatt 967*94de0730Smatt /* 968*94de0730Smatt * PINCTRL Drive Strength and Voltage Register 2. 969*94de0730Smatt */ 970*94de0730Smatt #define HW_PINCTRL_DRIVE2 0x220 971*94de0730Smatt #define HW_PINCTRL_DRIVE2_SET 0x224 972*94de0730Smatt #define HW_PINCTRL_DRIVE2_CLR 0x228 973*94de0730Smatt #define HW_PINCTRL_DRIVE2_TOG 0x22C 974*94de0730Smatt 975*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD7 __BITS(31, 30) 976*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN23_MA __BITS(29, 28) 977*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD6 __BITS(27, 26) 978*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN22_MA __BITS(25, 24) 979*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD5 __BITS(23, 22) 980*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN21_MA __BITS(21, 20) 981*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD4 __BITS(19, 18) 982*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN20_MA __BITS(17, 16) 983*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD3 __BITS(15, 14) 984*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN19_MA __BITS(13, 12) 985*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD2 __BITS(11, 10) 986*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN18_MA __BITS(9, 8) 987*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD1 __BITS(7, 6) 988*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN17_MA __BITS(5, 4) 989*94de0730Smatt #define HW_PINCTRL_DRIVE2_RSRVD0 __BITS(3, 2) 990*94de0730Smatt #define HW_PINCTRL_DRIVE2_BANK0_PIN16_MA __BITS(1, 0) 991*94de0730Smatt 992*94de0730Smatt /* 993eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 8. 994eba5cacbSjkunz */ 995eba5cacbSjkunz #define HW_PINCTRL_DRIVE8 0x280 996eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_SET 0x284 997eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_CLR 0x288 998eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_TOG 0x28C 999eba5cacbSjkunz 1000eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD7 __BITS(31, 30) 1001eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN07_MA __BITS(29, 28) 1002eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD6 __BITS(27, 26) 1003eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN06_MA __BITS(25, 24) 1004eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD5 __BITS(23, 22) 1005eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN05_MA __BITS(21, 20) 1006eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD4 __BITS(19, 18) 1007eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN04_MA __BITS(17, 16) 1008eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD3 __BITS(15, 14) 1009eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN03_MA __BITS(13, 12) 1010eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD2 __BITS(11, 10) 1011eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN02_MA __BITS(9, 8) 1012eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD1 __BITS(7, 6) 1013eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN01_MA __BITS(5, 4) 1014eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_RSRVD0 __BITS(3, 2) 1015eba5cacbSjkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN00_MA __BITS(1, 0) 1016eba5cacbSjkunz 1017eba5cacbSjkunz /* 1018eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 9. 1019eba5cacbSjkunz */ 1020eba5cacbSjkunz #define HW_PINCTRL_DRIVE9 0x290 1021eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_SET 0x294 1022eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_CLR 0x298 1023eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_TOG 0x29C 1024eba5cacbSjkunz 1025eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD7 __BIT(31) 1026eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN15_V __BIT(30) 1027eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN15_MA __BITS(29, 28) 1028eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD6 __BIT(27) 1029eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN14_V __BIT(26) 1030eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN14_MA __BITS(25, 24) 1031eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD5 __BIT(23) 1032eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN13_V __BIT(22) 1033eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN13_MA __BITS(21, 20) 1034eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD4 __BIT(19) 1035eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN12_V __BIT(18) 1036eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN12_MA __BITS(17, 16) 1037eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD3 __BIT(15) 1038eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN11_V __BIT(14) 1039eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN11_MA __BITS(13, 12) 1040eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD2 __BIT(11) 1041eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN10_V __BIT(10) 1042eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN10_MA __BITS(9, 8) 1043eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD1 __BIT(7) 1044eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN09_V __BIT(6) 1045eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN09_MA __BITS(5, 4) 1046eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_RSRVD0 __BITS(3, 2) 1047eba5cacbSjkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN08_MA __BITS(1, 0) 1048eba5cacbSjkunz 1049eba5cacbSjkunz /* 1050eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 10. 1051eba5cacbSjkunz */ 1052eba5cacbSjkunz #define HW_PINCTRL_DRIVE10 0x2a0 1053eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_SET 0x2a4 1054eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_CLR 0x2a8 1055eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_TOG 0x2ac 1056eba5cacbSjkunz 1057eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD7 __BIT(31) 1058eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN23_V __BIT(30) 1059eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN23_MA __BITS(29, 28) 1060eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD6 __BIT(27) 1061eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN22_V __BIT(26) 1062eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN22_MA __BITS(25, 24) 1063eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD5 __BIT(23) 1064eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN21_V __BIT(22) 1065eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN21_MA __BITS(21, 20) 1066eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD4 __BIT(19) 1067eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN20_V __BIT(18) 1068eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN20_MA __BITS(17, 16) 1069eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD3 __BIT(15) 1070eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN19_V __BIT(14) 1071eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN19_MA __BITS(13, 12) 1072eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD2 __BIT(11) 1073eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN18_V __BIT(10) 1074eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN18_MA __BITS(9, 8) 1075eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD1 __BIT(7) 1076eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN17_V __BIT(6) 1077eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN17_MA __BITS(5, 4) 1078eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_RSRVD0 __BIT(3) 1079eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN16_V __BIT(2) 1080eba5cacbSjkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN16_MA __BITS(1, 0) 1081eba5cacbSjkunz 1082eba5cacbSjkunz /* 1083eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 11. 1084eba5cacbSjkunz */ 1085eba5cacbSjkunz #define HW_PINCTRL_DRIVE11 0x2b0 1086eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_SET 0x2b4 1087eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_CLR 0x2b8 1088eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_TOG 0x2bC 1089eba5cacbSjkunz 1090eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD7 __BIT(31) 1091eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN31_V __BIT(30) 1092eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN31_MA __BITS(29, 28) 1093eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD6 __BIT(27) 1094eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN30_V __BIT(26) 1095eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN30_MA __BITS(25, 24) 1096eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD5 __BIT(23) 1097eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN29_V __BIT(22) 1098eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN29_MA __BITS(21, 20) 1099eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD4 __BITS(19, 18) 1100eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN28_MA __BIT(17, 16) 1101eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD3 __BITS(15, 14) 1102eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN27_MA __BITS(13, 12) 1103eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD2 __BIT(11) 1104eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN26_V __BIT(10) 1105eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN26_MA __BITS(9, 8) 1106eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD1 __BIT(7) 1107eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN25_V __BIT(6) 1108eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN25_MA __BITS(5, 4) 1109eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_RSRVD0 __BIT(3) 1110eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN24_V __BIT(2) 1111eba5cacbSjkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN24_MA __BITS(1, 0) 1112eba5cacbSjkunz 1113eba5cacbSjkunz /* 1114eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 12. 1115eba5cacbSjkunz */ 1116eba5cacbSjkunz #define HW_PINCTRL_DRIVE12 0x2c0 1117eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_SET 0x2c4 1118eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_CLR 0x2c8 1119eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_TOG 0x2cC 1120eba5cacbSjkunz 1121eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD7 __BIT(31) 1122eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN07_V __BIT(30) 1123eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN07_MA __BITS(29, 28) 1124eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD6 __BIT(27) 1125eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN06_V __BIT(26) 1126eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN06_MA __BITS(25, 24) 1127eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD5 __BIT(23) 1128eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN05_V __BIT(22) 1129eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN05_MA __BITS(21, 20) 1130eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD4 __BIT(19) 1131eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN04_V __BIT(18) 1132eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN04_MA __BITS(17, 15) 1133eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD3 __BIT(15) 1134eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN03_V __BIT(14) 1135eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN03_MA __BITS(13, 12) 1136eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD2 __BIT(11) 1137eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN02_V __BIT(10) 1138eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN02_MA __BITS(9, 8) 1139eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD1 __BIT(7) 1140eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN01_V __BIT(6) 1141eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN01_MA __BITS(5, 4) 1142eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_RSRVD0 __BIT(3) 1143eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN00_V __BIT(2) 1144eba5cacbSjkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN00_MA __BITS(1, 0) 1145eba5cacbSjkunz 1146eba5cacbSjkunz /* 1147eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 13. 1148eba5cacbSjkunz */ 1149eba5cacbSjkunz #define HW_PINCTRL_DRIVE13 0x2d0 1150eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_SET 0x2d4 1151eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_CLR 0x2d8 1152eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_TOG 0x2dc 1153eba5cacbSjkunz 1154eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD7 __BIT(31) 1155eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN15_V __BIT(30) 1156eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN15_MA __BITS(29, 28) 1157eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD6 __BIT(27) 1158eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN14_V __BIT(26) 1159eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN14_MA __BITS(25, 24) 1160eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD5 __BIT(23) 1161eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN13_V __BIT(22) 1162eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN13_MA __BITS(21, 20) 1163eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD4 __BIT(19) 1164eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN12_V __BIT(18) 1165eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN12_MA __BITS(17, 16) 1166eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD3 __BIT(15) 1167eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN11_V __BIT(14) 1168eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN11_MA __BITS(13, 12) 1169eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD2 __BIT(11) 1170eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN10_V __BIT(10) 1171eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN10_MA __BITS(9, 8) 1172eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD1 __BIT(7) 1173eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN09_V __BIT(6) 1174eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN09_MA __BITS(5, 4) 1175eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_RSRVD0 __BIT(3) 1176eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN08_V __BIT(2) 1177eba5cacbSjkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN08_MA __BITS(1, 0) 1178eba5cacbSjkunz 1179eba5cacbSjkunz /* 1180eba5cacbSjkunz * PINCTRL Drive Strength and Voltage Register 14. 1181eba5cacbSjkunz */ 1182eba5cacbSjkunz #define HW_PINCTRL_DRIVE14 0x2e0 1183eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_SET 0x2e4 1184eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_CLR 0x2e8 1185eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_TOG 0x2ec 1186eba5cacbSjkunz 1187eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD6 __BITS(31, 24) 1188eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD5 __BIT(23) 1189eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN21_V __BIT(22) 1190eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN21_MA __BITS(21, 20) 1191eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD4 __BIT(19) 1192eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN20_V __BIT(18) 1193eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN20_MA __BITS(17, 16) 1194eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD3 __BIT(15) 1195eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN19_V __BIT(14) 1196eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN19_MA __BITS(13, 12) 1197eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD2 __BIT(11) 1198eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN18_V __BIT(10) 1199eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN18_MA __BITS(9, 8) 1200eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD1 __BIT(7) 1201eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN17_V __BIT(6) 1202eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN17_MA __BITS(5, 4) 1203eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_RSRVD0 __BIT(3) 1204eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN16_V __BIT(2) 1205eba5cacbSjkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN16_MA __BITS(1, 0) 1206eba5cacbSjkunz 1207eba5cacbSjkunz /* 1208*94de0730Smatt * PINCTRL Bank 0 Pull Up Resistor Enable Register. 1209*94de0730Smatt */ 1210*94de0730Smatt #define HW_PINCTRL_PULL0 0x400 1211*94de0730Smatt #define HW_PINCTRL_PULL0_SET 0x404 1212*94de0730Smatt #define HW_PINCTRL_PULL0_CLR 0x408 1213*94de0730Smatt #define HW_PINCTRL_PULL0_TOG 0x40C 1214*94de0730Smatt 1215*94de0730Smatt /* 1216eba5cacbSjkunz * PINCTRL Bank 2 Pull Up Resistor Enable Register. 1217eba5cacbSjkunz */ 1218eba5cacbSjkunz #define HW_PINCTRL_PULL2 0x420 1219eba5cacbSjkunz #define HW_PINCTRL_PULL2_SET 0x424 1220eba5cacbSjkunz #define HW_PINCTRL_PULL2_CLR 0x428 1221eba5cacbSjkunz #define HW_PINCTRL_PULL2_TOG 0x42C 1222eba5cacbSjkunz 1223eba5cacbSjkunz #define HW_PINCTRL_PULL2_RSRVD2 __BITS(31, 29) 1224eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN28 __BIT(28) 1225eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN27 __BIT(27) 1226eba5cacbSjkunz #define HW_PINCTRL_PULL2_RSRVD1 __BITS(26, 9) 1227eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN08 __BIT(8) 1228eba5cacbSjkunz #define HW_PINCTRL_PULL2_RSRVD0 __BITS(7, 6) 1229eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN05 __BIT(5) 1230eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN04 __BIT(4) 1231eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN03 __BIT(3) 1232eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN02 __BIT(2) 1233eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN01 __BIT(1) 1234eba5cacbSjkunz #define HW_PINCTRL_PULL2_BANK2_PIN00 __BIT(0) 1235eba5cacbSjkunz 1236eba5cacbSjkunz /* 1237eba5cacbSjkunz * PINCTRL Bank 3 Pad Keeper Disable Register. 1238eba5cacbSjkunz */ 1239eba5cacbSjkunz #define HW_PINCTRL_PULL3 0x430 1240eba5cacbSjkunz #define HW_PINCTRL_PULL3_SET 0x434 1241eba5cacbSjkunz #define HW_PINCTRL_PULL3_CLR 0x438 1242eba5cacbSjkunz #define HW_PINCTRL_PULL3_TOG 0x43C 1243eba5cacbSjkunz 1244eba5cacbSjkunz #define HW_PINCTRL_PULL3_RSRVD0 __BITS(31, 18) 1245eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN17 __BIT(17) 1246eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN16 __BIT(16) 1247eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN15 __BIT(15) 1248eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN14 __BIT(14) 1249eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN13 __BIT(13) 1250eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN12 __BIT(12) 1251eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN11 __BIT(11) 1252eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN10 __BIT(10) 1253eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN09 __BIT(9) 1254eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN08 __BIT(8) 1255eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN07 __BIT(7) 1256eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN06 __BIT(6) 1257eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN05 __BIT(5) 1258eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN04 __BIT(4) 1259eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN03 __BIT(3) 1260eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN02 __BIT(2) 1261eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN01 __BIT(1) 1262eba5cacbSjkunz #define HW_PINCTRL_PULL3_BANK3_PIN00 __BIT(0) 1263eba5cacbSjkunz 1264*94de0730Smatt /* 1265*94de0730Smatt * PINCTRL Bank 0 Data Output Register. 1266*94de0730Smatt */ 1267*94de0730Smatt #define HW_PINCTRL_DOUT0 0x500 1268*94de0730Smatt #define HW_PINCTRL_DOUT0_SET 0x504 1269*94de0730Smatt #define HW_PINCTRL_DOUT0_CLR 0x508 1270*94de0730Smatt #define HW_PINCTRL_DOUT0_TOG 0x50C 1271*94de0730Smatt 1272*94de0730Smatt #define HW_PINCTRL_DOUT0_DOUT __BITS(31, 0) 1273*94de0730Smatt 1274*94de0730Smatt /* 1275*94de0730Smatt * PINCTRL Bank 1 Data Output Register. 1276*94de0730Smatt */ 1277*94de0730Smatt #define HW_PINCTRL_DOUT1 0x510 1278*94de0730Smatt #define HW_PINCTRL_DOUT1_SET 0x514 1279*94de0730Smatt #define HW_PINCTRL_DOUT1_CLR 0x518 1280*94de0730Smatt #define HW_PINCTRL_DOUT1_TOG 0x51C 1281*94de0730Smatt 1282*94de0730Smatt #define HW_PINCTRL_DOUT1_DOUT __BITS(31, 0) 1283*94de0730Smatt 1284*94de0730Smatt /* 1285*94de0730Smatt * PINCTRL Bank 0 Data Input Register. 1286*94de0730Smatt */ 1287*94de0730Smatt #define HW_PINCTRL_DIN0 0x600 1288*94de0730Smatt #define HW_PINCTRL_DIN0_SET 0x604 1289*94de0730Smatt #define HW_PINCTRL_DIN0_CLR 0x608 1290*94de0730Smatt #define HW_PINCTRL_DIN0_TOG 0x60C 1291*94de0730Smatt 1292*94de0730Smatt /* 1293*94de0730Smatt * PINCTRL Bank 0 Data Output Enable Register. 1294*94de0730Smatt */ 1295*94de0730Smatt #define HW_PINCTRL_DOE0 0x700 1296*94de0730Smatt #define HW_PINCTRL_DOE0_SET 0x704 1297*94de0730Smatt #define HW_PINCTRL_DOE0_CLR 0x708 1298*94de0730Smatt #define HW_PINCTRL_DOE0_TOG 0x70C 1299*94de0730Smatt 1300*94de0730Smatt #define HW_PINCTRL_DOE0_DOE __BITS(31, 0) 1301*94de0730Smatt 1302eba5cacbSjkunz #endif /* !_ARM_IMX_IMX23_PINCTRLREG_H_ */ 1303