1 /* $NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.40 2019/06/16 10:57:59 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/percpu.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/locore.h> 48 #include <arm/cpufunc.h> 49 50 #include <arm/cortex/gtmr_var.h> 51 #include <arm/cortex/mpcore_var.h> 52 53 static int gtmr_match(device_t, cfdata_t, void *); 54 static void gtmr_attach(device_t, device_t, void *); 55 56 static u_int gtmr_get_timecount(struct timecounter *); 57 58 static struct gtmr_softc gtmr_sc; 59 60 struct gtmr_percpu { 61 uint32_t pc_delta; 62 }; 63 64 static struct timecounter gtmr_timecounter = { 65 .tc_get_timecount = gtmr_get_timecount, 66 .tc_poll_pps = 0, 67 .tc_counter_mask = ~0u, 68 .tc_frequency = 0, /* set by cpu_initclocks() */ 69 .tc_name = NULL, /* set by attach */ 70 .tc_quality = 500, 71 .tc_priv = >mr_sc, 72 .tc_next = NULL, 73 }; 74 75 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 76 77 /* ARGSUSED */ 78 static int 79 gtmr_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 struct mpcore_attach_args * const mpcaa = aux; 82 83 if (gtmr_sc.sc_dev != NULL) 84 return 0; 85 86 /* Generic Timer is always implemented in ARMv8-A */ 87 if (!cpu_gtmr_exists_p()) 88 return 0; 89 90 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 91 return 0; 92 93 return 1; 94 } 95 96 static void 97 gtmr_attach(device_t parent, device_t self, void *aux) 98 { 99 struct mpcore_attach_args * const mpcaa = aux; 100 struct gtmr_softc *sc = >mr_sc; 101 prop_dictionary_t dict = device_properties(self); 102 char freqbuf[sizeof("X.XXX SHz")]; 103 bool flag; 104 105 /* 106 * This runs at a fixed frequency of 1 to 50MHz. 107 */ 108 if (!prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq)) 109 sc->sc_freq = gtmr_cntfrq_read(); 110 111 KASSERT(sc->sc_freq != 0); 112 113 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 114 115 aprint_naive("\n"); 116 aprint_normal(": ARM Generic Timer (%s)\n", freqbuf); 117 118 if (prop_dictionary_get_bool(dict, "sun50i-a64-unstable-timer", &flag) && flag) { 119 sc->sc_flags |= GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER; 120 aprint_debug_dev(self, "enabling Allwinner A64 timer workaround\n"); 121 } 122 123 self->dv_private = sc; 124 sc->sc_dev = self; 125 126 #ifdef DIAGNOSTIC 127 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 128 #endif 129 130 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 131 device_xname(self), "missing interrupts"); 132 133 if (mpcaa->mpcaa_irq != -1) { 134 sc->sc_global_ih = intr_establish(mpcaa->mpcaa_irq, IPL_CLOCK, 135 IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL); 136 if (sc->sc_global_ih == NULL) 137 panic("%s: unable to register timer interrupt", __func__); 138 aprint_normal_dev(self, "interrupting on irq %d\n", 139 mpcaa->mpcaa_irq); 140 } 141 142 const uint32_t cnt_frq = gtmr_cntfrq_read(); 143 if (cnt_frq == 0) { 144 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 145 } else if (cnt_frq != sc->sc_freq) { 146 aprint_verbose_dev(self, 147 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 148 cnt_frq); 149 } 150 151 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 152 gtmr_timecounter.tc_frequency = sc->sc_freq; 153 gtmr_timecounter.tc_priv = sc; 154 155 tc_init(>mr_timecounter); 156 157 /* Disable the timer until we are ready */ 158 gtmr_cntv_ctl_write(0); 159 } 160 161 static uint64_t 162 gtmr_read_cntvct(struct gtmr_softc *sc) 163 { 164 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 165 /* 166 * The Allwinner A64 SoC has an unstable architectural timer. 167 * To workaround this problem, ignore reads where the lower 168 * 11 bits are all 0s or 1s. 169 */ 170 uint64_t val; 171 u_int bits; 172 do { 173 val = gtmr_cntvct_read(); 174 bits = val & __BITS(9,0); 175 } while (bits == 0 || bits == __BITS(9,0)); 176 return val; 177 } 178 179 return gtmr_cntvct_read(); 180 } 181 182 void 183 gtmr_init_cpu_clock(struct cpu_info *ci) 184 { 185 struct gtmr_softc * const sc = >mr_sc; 186 187 KASSERT(ci == curcpu()); 188 189 int s = splsched(); 190 191 /* 192 * Allow the virtual and physical counters to be accessed from 193 * usermode. (PL0) 194 */ 195 gtmr_cntk_ctl_write(gtmr_cntk_ctl_read() | 196 CNTKCTL_PL0VCTEN | CNTKCTL_PL0PCTEN); 197 198 /* 199 * enable timer and stop masking the timer. 200 */ 201 gtmr_cntv_ctl_write(CNTCTL_ENABLE); 202 203 /* 204 * Get now and update the compare timer. 205 */ 206 arm_isb(); 207 ci->ci_lastintr = gtmr_read_cntvct(sc); 208 gtmr_cntv_tval_write(sc->sc_autoinc); 209 splx(s); 210 KASSERT(gtmr_read_cntvct(sc) != 0); 211 } 212 213 void 214 gtmr_cpu_initclocks(void) 215 { 216 struct gtmr_softc * const sc = >mr_sc; 217 218 KASSERT(sc->sc_dev != NULL); 219 KASSERT(sc->sc_freq != 0); 220 221 sc->sc_autoinc = sc->sc_freq / hz; 222 223 gtmr_init_cpu_clock(curcpu()); 224 } 225 226 void 227 gtmr_delay(unsigned int n) 228 { 229 struct gtmr_softc * const sc = >mr_sc; 230 231 KASSERT(sc != NULL); 232 233 uint32_t freq = sc->sc_freq ? sc->sc_freq : gtmr_cntfrq_read(); 234 KASSERT(freq != 0); 235 236 const unsigned int incr_per_us = howmany(freq, 1000000); 237 int64_t ticks = (int64_t)n * incr_per_us; 238 239 arm_isb(); 240 uint64_t last = gtmr_read_cntvct(sc); 241 242 while (ticks > 0) { 243 arm_isb(); 244 uint64_t curr = gtmr_read_cntvct(sc); 245 if (curr >= last) 246 ticks -= (curr - last); 247 else 248 ticks -= (UINT64_MAX - curr + last); 249 last = curr; 250 } 251 } 252 253 /* 254 * gtmr_intr: 255 * 256 * Handle the hardclock interrupt. 257 */ 258 int 259 gtmr_intr(void *arg) 260 { 261 struct cpu_info * const ci = curcpu(); 262 struct clockframe * const cf = arg; 263 struct gtmr_softc * const sc = >mr_sc; 264 265 arm_isb(); 266 267 const uint32_t ctl = gtmr_cntv_ctl_read(); 268 if ((ctl & CNTCTL_ISTATUS) == 0) 269 return 0; 270 271 arm_isb(); 272 gtmr_cntv_ctl_write(0); 273 274 const uint64_t now = gtmr_read_cntvct(sc); 275 uint64_t delta = now - ci->ci_lastintr; 276 277 #ifdef DIAGNOSTIC 278 struct gtmr_percpu *pc = NULL; 279 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 280 const uint64_t then = gtmr_cntv_cval_read(); 281 pc = percpu_getref(sc->sc_percpu); 282 KASSERTMSG(then <= now, "%"PRId64, now - then); 283 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 284 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 285 } 286 #endif 287 288 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 289 KASSERTMSG(delta > sc->sc_autoinc / 100, 290 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 291 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 292 } 293 294 /* 295 * If we got interrupted too soon (delta < sc->sc_autoinc) 296 * or we missed (or almost missed) a tick 297 * (delta >= 7 * sc->sc_autoinc / 4), don't try to adjust for jitter. 298 */ 299 if (delta >= sc->sc_autoinc && delta <= 7 * sc->sc_autoinc / 4) { 300 delta -= sc->sc_autoinc; 301 } else { 302 delta = 0; 303 } 304 305 arm_isb(); 306 if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 307 gtmr_cntv_cval_write(now + sc->sc_autoinc - delta); 308 } else { 309 gtmr_cntv_tval_write(sc->sc_autoinc - delta); 310 } 311 312 arm_isb(); 313 gtmr_cntv_ctl_write(CNTCTL_ENABLE); 314 315 ci->ci_lastintr = now; 316 317 #ifdef DIAGNOSTIC 318 if (!ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) { 319 KASSERT(delta == (uint32_t) delta); 320 pc->pc_delta = delta; 321 percpu_putref(sc->sc_percpu); 322 } 323 #endif 324 325 hardclock(cf); 326 327 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 328 329 return 1; 330 } 331 332 void 333 setstatclockrate(int newhz) 334 { 335 } 336 337 static u_int 338 gtmr_get_timecount(struct timecounter *tc) 339 { 340 struct gtmr_softc * const sc = tc->tc_priv; 341 arm_isb(); // we want the time NOW, not some instructions later. 342 return (u_int) gtmr_read_cntvct(sc); 343 } 344