1 /* $NetBSD: gtmr.c,v 1.8 2014/06/11 05:50:46 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.8 2014/06/11 05:50:46 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/kernel.h> 40 #include <sys/percpu.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 45 #include <prop/proplib.h> 46 47 #include <arm/cortex/gtmr_var.h> 48 49 #include <arm/cortex/mpcore_var.h> 50 51 static int gtmr_match(device_t, cfdata_t, void *); 52 static void gtmr_attach(device_t, device_t, void *); 53 54 static int gtmr_intr(void *); 55 56 static u_int gtmr_get_timecount(struct timecounter *); 57 58 static struct gtmr_softc gtmr_sc; 59 60 struct gtmr_percpu { 61 uint32_t pc_delta; 62 }; 63 64 static struct timecounter gtmr_timecounter = { 65 .tc_get_timecount = gtmr_get_timecount, 66 .tc_poll_pps = 0, 67 .tc_counter_mask = ~0u, 68 .tc_frequency = 0, /* set by cpu_initclocks() */ 69 .tc_name = NULL, /* set by attach */ 70 .tc_quality = 500, 71 .tc_priv = >mr_sc, 72 .tc_next = NULL, 73 }; 74 75 CFATTACH_DECL_NEW(armgtmr, 0, gtmr_match, gtmr_attach, NULL, NULL); 76 77 /* ARGSUSED */ 78 static int 79 gtmr_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 struct mpcore_attach_args * const mpcaa = aux; 82 83 if (gtmr_sc.sc_dev != NULL) 84 return 0; 85 86 if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) == 0) 87 return 0; 88 89 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 90 return 0; 91 92 return 1; 93 } 94 95 static void 96 gtmr_attach(device_t parent, device_t self, void *aux) 97 { 98 struct gtmr_softc *sc = >mr_sc; 99 prop_dictionary_t dict = device_properties(self); 100 char freqbuf[sizeof("X.XXX SHz")]; 101 102 /* 103 * This runs at a fixed frequency of 1 to 50MHz. 104 */ 105 prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq); 106 KASSERT(sc->sc_freq != 0); 107 108 humanize_number(freqbuf, sizeof(freqbuf), sc->sc_freq, "Hz", 1000); 109 110 aprint_naive("\n"); 111 aprint_normal(": ARMv7 Generic 64-bit Timer (%s)\n", freqbuf); 112 113 /* 114 * Enable the virtual counter to be accessed from usermode. 115 */ 116 armreg_cntk_ctl_write(armreg_cntk_ctl_read() | ARM_CNTKCTL_PL0VCTEN); 117 118 self->dv_private = sc; 119 sc->sc_dev = self; 120 121 #ifdef DIAGNOSTIC 122 sc->sc_percpu = percpu_alloc(sizeof(struct gtmr_percpu)); 123 #endif 124 125 evcnt_attach_dynamic(&sc->sc_ev_missing_ticks, EVCNT_TYPE_MISC, NULL, 126 device_xname(self), "missing interrupts"); 127 128 sc->sc_global_ih = intr_establish(IRQ_GTMR_PPI_VTIMER, IPL_CLOCK, 129 IST_EDGE | IST_MPSAFE, gtmr_intr, NULL); 130 if (sc->sc_global_ih == NULL) 131 panic("%s: unable to register timer interrupt", __func__); 132 aprint_normal_dev(self, "interrupting on irq %d\n", 133 IRQ_GTMR_PPI_VTIMER); 134 135 const uint32_t cnt_frq = armreg_cnt_frq_read(); 136 if (cnt_frq == 0) { 137 aprint_verbose_dev(self, "cp15 CNT_FRQ not set\n"); 138 } else if (cnt_frq != sc->sc_freq) { 139 aprint_verbose_dev(self, 140 "cp15 CNT_FRQ (%u) differs from supplied frequency\n", 141 cnt_frq); 142 } 143 144 gtmr_timecounter.tc_name = device_xname(sc->sc_dev); 145 gtmr_timecounter.tc_frequency = sc->sc_freq; 146 147 tc_init(>mr_timecounter); 148 } 149 150 void 151 gtmr_init_cpu_clock(struct cpu_info *ci) 152 { 153 struct gtmr_softc * const sc = >mr_sc; 154 155 KASSERT(ci == curcpu()); 156 157 int s = splsched(); 158 159 /* 160 * enable timer and stop masking the timer. 161 */ 162 armreg_cntv_ctl_write(ARM_CNTCTL_ENABLE); 163 #if 0 164 printf("%s: cntctl=%#x\n", __func__, armreg_cntv_ctl_read()); 165 #endif 166 167 /* 168 * Get now and update the compare timer. 169 */ 170 ci->ci_lastintr = armreg_cntv_ct_read(); 171 armreg_cntv_tval_write(sc->sc_autoinc); 172 #if 0 173 printf("%s: %s: delta cval = %"PRIu64"\n", 174 __func__, ci->ci_data.cpu_name, 175 armreg_cntv_cval_read() - ci->ci_lastintr); 176 #endif 177 splx(s); 178 KASSERT(armreg_cntv_ct_read() != 0); 179 #if 0 180 printf("%s: %s: ctl %#x cmp %#"PRIx64" now %#"PRIx64"\n", 181 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 182 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 183 184 s = splsched(); 185 186 uint64_t now64; 187 uint64_t start64 = armreg_cntv_ct_read(); 188 do { 189 now64 = armreg_cntv_ct_read(); 190 } while (start64 == now64); 191 start64 = now64; 192 uint64_t end64 = start64 + 64; 193 uint32_t start32 = armreg_pmccntr_read(); 194 do { 195 now64 = armreg_cntv_ct_read(); 196 } while (end64 != now64); 197 uint32_t end32 = armreg_pmccntr_read(); 198 199 uint32_t diff32 = end64 - start64; 200 printf("%s: %s: %u cycles per tick\n", 201 __func__, ci->ci_data.cpu_name, (end32 - start32) / diff32); 202 203 printf("%s: %s: status %#x cmp %#"PRIx64" now %#"PRIx64"\n", 204 __func__, ci->ci_data.cpu_name, armreg_cntv_ctl_read(), 205 armreg_cntv_cval_read(), armreg_cntv_ct_read()); 206 splx(s); 207 #elif 0 208 delay(1000000 / hz + 1000); 209 #endif 210 } 211 212 void 213 cpu_initclocks(void) 214 { 215 struct gtmr_softc * const sc = >mr_sc; 216 217 KASSERT(sc->sc_dev != NULL); 218 KASSERT(sc->sc_freq != 0); 219 220 sc->sc_autoinc = sc->sc_freq / hz; 221 222 gtmr_init_cpu_clock(curcpu()); 223 } 224 225 void 226 gtmr_delay(unsigned int n) 227 { 228 struct gtmr_softc * const sc = >mr_sc; 229 230 KASSERT(sc != NULL); 231 232 uint32_t freq = sc->sc_freq ? sc->sc_freq : armreg_cnt_frq_read(); 233 KASSERT(freq != 0); 234 235 /* 236 * not quite divide by 1000000 but close enough 237 * (higher by 1.3% which means we wait 1.3% longer). 238 */ 239 const uint64_t incr_per_us = (freq >> 20) + (freq >> 24); 240 241 const uint64_t delta = n * incr_per_us; 242 const uint64_t base = armreg_cntv_ct_read(); 243 const uint64_t finish = base + delta; 244 245 while (armreg_cntv_ct_read() < finish) { 246 /* spin */ 247 } 248 } 249 250 void 251 gtmr_bootdelay(unsigned int ticks) 252 { 253 const uint32_t ctl = armreg_cntv_ctl_read(); 254 armreg_cntv_ctl_write(ctl | ARM_CNTCTL_ENABLE | ARM_CNTCTL_IMASK); 255 256 /* Write Timer/Value to set new compare time */ 257 armreg_cntv_tval_write(ticks); 258 259 /* Spin until compare time is hit */ 260 while ((armreg_cntv_ctl_read() & ARM_CNTCTL_ISTATUS) == 0) { 261 /* spin */ 262 } 263 264 armreg_cntv_ctl_write(ctl); 265 } 266 267 /* 268 * gtmr_intr: 269 * 270 * Handle the hardclock interrupt. 271 */ 272 static int 273 gtmr_intr(void *arg) 274 { 275 const uint64_t now = armreg_cntv_ct_read(); 276 struct cpu_info * const ci = curcpu(); 277 uint64_t delta = now - ci->ci_lastintr; 278 struct clockframe * const cf = arg; 279 struct gtmr_softc * const sc = >mr_sc; 280 281 #ifdef DIAGNOSTIC 282 const uint64_t then = armreg_cntv_cval_read(); 283 struct gtmr_percpu * const pc = percpu_getref(sc->sc_percpu); 284 KASSERTMSG(then <= now, "%"PRId64, now - then); 285 KASSERTMSG(then + pc->pc_delta >= ci->ci_lastintr + sc->sc_autoinc, 286 "%"PRId64, then + pc->pc_delta - ci->ci_lastintr - sc->sc_autoinc); 287 #endif 288 289 #if 0 290 printf("%s(%p): %s: now %#"PRIx64" delta %"PRIu64"\n", 291 __func__, cf, ci->ci_data.cpu_name, now, delta); 292 #endif 293 KASSERTMSG(delta > sc->sc_autoinc / 100, 294 "%s: interrupting too quickly (delta=%"PRIu64") autoinc=%lu", 295 ci->ci_data.cpu_name, delta, sc->sc_autoinc); 296 297 /* 298 * If we got interrupted too soon (delta < sc->sc_autoinc) or 299 * we missed a tick (delta >= 2 * sc->sc_autoinc), don't try to 300 * adjust for jitter. 301 */ 302 delta -= sc->sc_autoinc; 303 if (delta >= sc->sc_autoinc) { 304 delta = 0; 305 } 306 armreg_cntv_tval_write(sc->sc_autoinc - delta); 307 308 ci->ci_lastintr = now; 309 310 #ifdef DIAGNOSTIC 311 KASSERT(delta == (uint32_t) delta); 312 pc->pc_delta = delta; 313 percpu_putref(sc->sc_percpu); 314 #endif 315 316 hardclock(cf); 317 318 sc->sc_ev_missing_ticks.ev_count += delta / sc->sc_autoinc; 319 320 return 1; 321 } 322 323 void 324 setstatclockrate(int newhz) 325 { 326 } 327 328 static u_int 329 gtmr_get_timecount(struct timecounter *tc) 330 { 331 332 return (u_int) (armreg_cntv_ct_read()); 333 } 334