1 /* $NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill@invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define _INTR_PRIVATE 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.21 2019/06/30 17:33:59 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/kmem.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/bitops.h> 42 43 #include <uvm/uvm.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <arm/pic/picvar.h> 49 #include <arm/cortex/gicv3_its.h> 50 51 /* 52 * ITS translation table sizes 53 */ 54 #define GITS_COMMANDS_SIZE 0x1000 55 #define GITS_COMMANDS_ALIGN 0x10000 56 57 #define GITS_ITT_ALIGN 0x100 58 59 /* 60 * IIDR values used for errata 61 */ 62 #define GITS_IIDR_PID_CAVIUM_THUNDERX 0xa1 63 #define GITS_IIDR_IMP_CAVIUM 0x34c 64 #define GITS_IIDR_CAVIUM_ERRATA_MASK (GITS_IIDR_Implementor|GITS_IIDR_ProductID|GITS_IIDR_Variant) 65 #define GITS_IIDR_CAVIUM_ERRATA_VALUE \ 66 (__SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) | \ 67 __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) | \ 68 __SHIFTIN(0, GITS_IIDR_Variant)) 69 70 static const char * gits_cache_type[] = { 71 [GITS_Cache_DEVICE_nGnRnE] = "Device-nGnRnE", 72 [GITS_Cache_NORMAL_NC] = "Non-cacheable", 73 [GITS_Cache_NORMAL_RA_WT] = "Cacheable RA WT", 74 [GITS_Cache_NORMAL_RA_WB] = "Cacheable RA WB", 75 [GITS_Cache_NORMAL_WA_WT] = "Cacheable WA WT", 76 [GITS_Cache_NORMAL_WA_WB] = "Cacheable WA WB", 77 [GITS_Cache_NORMAL_RA_WA_WT] = "Cacheable RA WA WT", 78 [GITS_Cache_NORMAL_RA_WA_WB] = "Cacheable RA WA WB", 79 }; 80 81 static const char * gits_share_type[] = { 82 [GITS_Shareability_NS] = "Non-shareable", 83 [GITS_Shareability_IS] = "Inner shareable", 84 [GITS_Shareability_OS] = "Outer shareable", 85 [3] = "(Reserved)", 86 }; 87 88 static inline uint32_t 89 gits_read_4(struct gicv3_its *its, bus_size_t reg) 90 { 91 return bus_space_read_4(its->its_bst, its->its_bsh, reg); 92 } 93 94 static inline void 95 gits_write_4(struct gicv3_its *its, bus_size_t reg, uint32_t val) 96 { 97 bus_space_write_4(its->its_bst, its->its_bsh, reg, val); 98 } 99 100 static inline uint64_t 101 gits_read_8(struct gicv3_its *its, bus_size_t reg) 102 { 103 return bus_space_read_8(its->its_bst, its->its_bsh, reg); 104 } 105 106 static inline void 107 gits_write_8(struct gicv3_its *its, bus_size_t reg, uint64_t val) 108 { 109 bus_space_write_8(its->its_bst, its->its_bsh, reg, val); 110 } 111 112 static inline void 113 gits_command(struct gicv3_its *its, const struct gicv3_its_command *cmd) 114 { 115 uint64_t cwriter; 116 u_int woff; 117 118 cwriter = gits_read_8(its, GITS_CWRITER); 119 woff = cwriter & GITS_CWRITER_Offset; 120 121 memcpy(its->its_cmd.base + woff, cmd->dw, sizeof(cmd->dw)); 122 bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); 123 124 woff += sizeof(cmd->dw); 125 if (woff == its->its_cmd.len) 126 woff = 0; 127 128 gits_write_8(its, GITS_CWRITER, woff); 129 } 130 131 static inline void 132 gits_command_mapc(struct gicv3_its *its, uint16_t icid, uint64_t rdbase, bool v) 133 { 134 struct gicv3_its_command cmd; 135 136 KASSERT((rdbase & 0xffff) == 0); 137 138 /* 139 * Map a collection table entry (ICID) to the target redistributor (RDbase). 140 */ 141 memset(&cmd, 0, sizeof(cmd)); 142 cmd.dw[0] = GITS_CMD_MAPC; 143 cmd.dw[2] = icid; 144 if (v) { 145 cmd.dw[2] |= rdbase; 146 cmd.dw[2] |= __BIT(63); 147 } 148 149 gits_command(its, &cmd); 150 } 151 152 static inline void 153 gits_command_mapd(struct gicv3_its *its, uint32_t deviceid, uint64_t itt_addr, u_int size, bool v) 154 { 155 struct gicv3_its_command cmd; 156 157 KASSERT((itt_addr & 0xff) == 0); 158 159 /* 160 * Map a device table entry (DeviceID) to its associated ITT (ITT_addr). 161 */ 162 memset(&cmd, 0, sizeof(cmd)); 163 cmd.dw[0] = GITS_CMD_MAPD | ((uint64_t)deviceid << 32); 164 cmd.dw[1] = size; 165 if (v) { 166 cmd.dw[2] = itt_addr | __BIT(63); 167 } 168 169 gits_command(its, &cmd); 170 } 171 172 static inline void 173 gits_command_mapti(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint32_t pintid, uint16_t icid) 174 { 175 struct gicv3_its_command cmd; 176 177 /* 178 * Map the event defined by EventID and DeviceID to its associated ITE, defined by ICID and pINTID 179 * in the ITT associated with DeviceID. 180 */ 181 memset(&cmd, 0, sizeof(cmd)); 182 cmd.dw[0] = GITS_CMD_MAPTI | ((uint64_t)deviceid << 32); 183 cmd.dw[1] = eventid | ((uint64_t)pintid << 32); 184 cmd.dw[2] = icid; 185 186 gits_command(its, &cmd); 187 } 188 189 static inline void 190 gits_command_movi(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint16_t icid) 191 { 192 struct gicv3_its_command cmd; 193 194 /* 195 * Update the ICID field in the ITT entry for the event defined by DeviceID and 196 * EventID. 197 */ 198 memset(&cmd, 0, sizeof(cmd)); 199 cmd.dw[0] = GITS_CMD_MOVI | ((uint64_t)deviceid << 32); 200 cmd.dw[1] = eventid; 201 cmd.dw[2] = icid; 202 203 gits_command(its, &cmd); 204 } 205 206 static inline void 207 gits_command_inv(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid) 208 { 209 struct gicv3_its_command cmd; 210 211 /* 212 * Ensure any caching in the redistributors associated with the specified 213 * EventID is consistent with the LPI configuration tables. 214 */ 215 memset(&cmd, 0, sizeof(cmd)); 216 cmd.dw[0] = GITS_CMD_INV | ((uint64_t)deviceid << 32); 217 cmd.dw[1] = eventid; 218 219 gits_command(its, &cmd); 220 } 221 222 static inline void 223 gits_command_invall(struct gicv3_its *its, uint16_t icid) 224 { 225 struct gicv3_its_command cmd; 226 227 /* 228 * Ensure any caching associated with this ICID is consistent with LPI 229 * configuration tables for all redistributors. 230 */ 231 memset(&cmd, 0, sizeof(cmd)); 232 cmd.dw[0] = GITS_CMD_INVALL; 233 cmd.dw[2] = icid; 234 235 gits_command(its, &cmd); 236 } 237 238 static inline void 239 gits_command_sync(struct gicv3_its *its, uint64_t rdbase) 240 { 241 struct gicv3_its_command cmd; 242 243 KASSERT((rdbase & 0xffff) == 0); 244 245 /* 246 * Ensure all outstanding ITS operations associated with physical interrupts 247 * for the specified redistributor (RDbase) are globally observed before 248 * further ITS commands are executed. 249 */ 250 memset(&cmd, 0, sizeof(cmd)); 251 cmd.dw[0] = GITS_CMD_SYNC; 252 cmd.dw[2] = rdbase; 253 254 gits_command(its, &cmd); 255 } 256 257 static inline int 258 gits_wait(struct gicv3_its *its) 259 { 260 u_int woff, roff; 261 int retry = 100000; 262 263 /* 264 * The ITS command queue is empty when CWRITER and CREADR specify the 265 * same base address offset value. 266 */ 267 for (retry = 1000; retry > 0; retry--) { 268 woff = gits_read_8(its, GITS_CWRITER) & GITS_CWRITER_Offset; 269 roff = gits_read_8(its, GITS_CREADR) & GITS_CREADR_Offset; 270 if (woff == roff) 271 break; 272 delay(100); 273 } 274 if (retry == 0) { 275 device_printf(its->its_gic->sc_dev, "ITS command queue timeout\n"); 276 return ETIMEDOUT; 277 } 278 279 return 0; 280 } 281 282 static int 283 gicv3_its_msi_alloc_lpi(struct gicv3_its *its, 284 const struct pci_attach_args *pa) 285 { 286 struct pci_attach_args *new_pa; 287 int n; 288 289 for (n = 0; n < its->its_pic->pic_maxsources; n++) { 290 if (its->its_pa[n] == NULL) { 291 new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); 292 memcpy(new_pa, pa, sizeof(*new_pa)); 293 its->its_pa[n] = new_pa; 294 return n + its->its_pic->pic_irqbase; 295 } 296 } 297 298 return -1; 299 } 300 301 static void 302 gicv3_its_msi_free_lpi(struct gicv3_its *its, int lpi) 303 { 304 struct pci_attach_args *pa; 305 306 KASSERT(lpi >= its->its_pic->pic_irqbase); 307 308 pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 309 its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL; 310 kmem_free(pa, sizeof(*pa)); 311 } 312 313 static uint32_t 314 gicv3_its_devid(pci_chipset_tag_t pc, pcitag_t tag) 315 { 316 uint32_t devid; 317 int b, d, f; 318 319 pci_decompose_tag(pc, tag, &b, &d, &f); 320 321 devid = (b << 8) | (d << 3) | f; 322 323 return pci_get_devid(pc, devid); 324 } 325 326 static int 327 gicv3_its_device_map(struct gicv3_its *its, uint32_t devid, u_int count) 328 { 329 struct gicv3_its_device *dev; 330 u_int vectors; 331 332 vectors = MAX(2, count); 333 while (!powerof2(vectors)) 334 vectors++; 335 336 const uint64_t typer = gits_read_8(its, GITS_TYPER); 337 const u_int itt_entry_size = __SHIFTOUT(typer, GITS_TYPER_ITT_entry_size) + 1; 338 const u_int itt_size = roundup(vectors * itt_entry_size, GITS_ITT_ALIGN); 339 340 LIST_FOREACH(dev, &its->its_devices, dev_list) 341 if (dev->dev_id == devid) { 342 return itt_size <= dev->dev_size ? 0 : EEXIST; 343 } 344 345 dev = kmem_alloc(sizeof(*dev), KM_SLEEP); 346 dev->dev_id = devid; 347 dev->dev_size = itt_size; 348 gicv3_dma_alloc(its->its_gic, &dev->dev_itt, itt_size, GITS_ITT_ALIGN); 349 LIST_INSERT_HEAD(&its->its_devices, dev, dev_list); 350 351 /* 352 * Map the device to the ITT 353 */ 354 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 355 gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true); 356 gits_wait(its); 357 358 return 0; 359 } 360 361 static void 362 gicv3_its_msi_enable(struct gicv3_its *its, int lpi, int count) 363 { 364 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 365 pci_chipset_tag_t pc = pa->pa_pc; 366 pcitag_t tag = pa->pa_tag; 367 pcireg_t ctl; 368 int off; 369 370 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 371 panic("gicv3_its_msi_enable: device is not MSI-capable"); 372 373 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 374 ctl &= ~PCI_MSI_CTL_MME_MASK; 375 ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK); 376 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 377 378 const uint64_t addr = its->its_base + GITS_TRANSLATER; 379 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 380 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 381 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, 382 addr & 0xffffffff); 383 pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 384 (addr >> 32) & 0xffffffff); 385 pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, 386 lpi - its->its_pic->pic_irqbase); 387 } else { 388 pci_conf_write(pc, tag, off + PCI_MSI_MADDR, 389 addr & 0xffffffff); 390 pci_conf_write(pc, tag, off + PCI_MSI_MDATA, 391 lpi - its->its_pic->pic_irqbase); 392 } 393 ctl |= PCI_MSI_CTL_MSI_ENABLE; 394 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 395 } 396 397 static void 398 gicv3_its_msi_disable(struct gicv3_its *its, int lpi) 399 { 400 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 401 pci_chipset_tag_t pc = pa->pa_pc; 402 pcitag_t tag = pa->pa_tag; 403 pcireg_t ctl; 404 int off; 405 406 if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) 407 panic("gicv3_its_msi_enable: device is not MSI-capable"); 408 409 ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); 410 ctl &= ~PCI_MSI_CTL_MSI_ENABLE; 411 pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); 412 } 413 414 static void 415 gicv3_its_msix_enable(struct gicv3_its *its, int lpi, int msix_vec, 416 bus_space_tag_t bst, bus_space_handle_t bsh) 417 { 418 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 419 pci_chipset_tag_t pc = pa->pa_pc; 420 pcitag_t tag = pa->pa_tag; 421 pcireg_t ctl; 422 int off; 423 424 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 425 panic("gicv3_its_msix_enable: device is not MSI-X-capable"); 426 427 const uint64_t addr = its->its_base + GITS_TRANSLATER; 428 const uint64_t entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec; 429 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); 430 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); 431 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); 432 bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); 433 434 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 435 ctl |= PCI_MSIX_CTL_ENABLE; 436 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 437 } 438 439 static void 440 gicv3_its_msix_disable(struct gicv3_its *its, int lpi) 441 { 442 const struct pci_attach_args *pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 443 pci_chipset_tag_t pc = pa->pa_pc; 444 pcitag_t tag = pa->pa_tag; 445 pcireg_t ctl; 446 int off; 447 448 if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL)) 449 panic("gicv3_its_msix_disable: device is not MSI-X-capable"); 450 451 ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); 452 ctl &= ~PCI_MSIX_CTL_ENABLE; 453 pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl); 454 } 455 456 static pci_intr_handle_t * 457 gicv3_its_msi_alloc(struct arm_pci_msi *msi, int *count, 458 const struct pci_attach_args *pa, bool exact) 459 { 460 struct gicv3_its * const its = msi->msi_priv; 461 struct cpu_info * const ci = cpu_lookup(0); 462 pci_intr_handle_t *vectors; 463 int n, off; 464 465 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL)) 466 return NULL; 467 468 const uint64_t typer = gits_read_8(its, GITS_TYPER); 469 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 470 if (*count == 0 || *count > (1 << id_bits)) 471 return NULL; 472 473 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 474 475 if (gicv3_its_device_map(its, devid, *count) != 0) 476 return NULL; 477 478 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 479 for (n = 0; n < *count; n++) { 480 const int lpi = gicv3_its_msi_alloc_lpi(its, pa); 481 vectors[n] = ARM_PCI_INTR_MSI | 482 __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) | 483 __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | 484 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 485 486 if (n == 0) 487 gicv3_its_msi_enable(its, lpi, *count); 488 489 /* 490 * Record target PE 491 */ 492 its->its_targets[lpi - its->its_pic->pic_irqbase] = ci; 493 494 /* 495 * Map event 496 */ 497 gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci)); 498 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 499 } 500 gits_wait(its); 501 502 return vectors; 503 } 504 505 static pci_intr_handle_t * 506 gicv3_its_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, int *count, 507 const struct pci_attach_args *pa, bool exact) 508 { 509 struct gicv3_its * const its = msi->msi_priv; 510 struct cpu_info *ci = cpu_lookup(0); 511 pci_intr_handle_t *vectors; 512 bus_space_tag_t bst; 513 bus_space_handle_t bsh; 514 bus_size_t bsz; 515 uint32_t table_offset, table_size; 516 int n, off, bar, error; 517 pcireg_t tbl; 518 519 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL)) 520 return NULL; 521 522 const uint64_t typer = gits_read_8(its, GITS_TYPER); 523 const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1; 524 if (*count == 0 || *count > (1 << id_bits)) 525 return NULL; 526 527 tbl = pci_conf_read(pa->pa_pc, pa->pa_tag, off + PCI_MSIX_TBLOFFSET); 528 bar = PCI_BAR0 + (4 * (tbl & PCI_MSIX_PBABIR_MASK)); 529 table_offset = tbl & PCI_MSIX_TBLOFFSET_MASK; 530 table_size = pci_msix_count(pa->pa_pc, pa->pa_tag) * PCI_MSIX_TABLE_ENTRY_SIZE; 531 if (table_size == 0) 532 return NULL; 533 534 error = pci_mapreg_submap(pa, bar, pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar), 535 BUS_SPACE_MAP_LINEAR, roundup(table_size, PAGE_SIZE), table_offset, 536 &bst, &bsh, NULL, &bsz); 537 if (error) 538 return NULL; 539 540 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 541 542 if (gicv3_its_device_map(its, devid, *count) != 0) { 543 bus_space_unmap(bst, bsh, bsz); 544 return NULL; 545 } 546 547 vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); 548 for (n = 0; n < *count; n++) { 549 const int lpi = gicv3_its_msi_alloc_lpi(its, pa); 550 const int msix_vec = table_indexes ? table_indexes[n] : n; 551 vectors[msix_vec] = ARM_PCI_INTR_MSIX | 552 __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) | 553 __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) | 554 __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); 555 556 gicv3_its_msix_enable(its, lpi, msix_vec, bst, bsh); 557 558 /* 559 * Record target PE 560 */ 561 its->its_targets[lpi - its->its_pic->pic_irqbase] = ci; 562 563 /* 564 * Map event 565 */ 566 gits_command_mapti(its, devid, lpi - its->its_pic->pic_irqbase, lpi, cpu_index(ci)); 567 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 568 } 569 gits_wait(its); 570 571 bus_space_unmap(bst, bsh, bsz); 572 573 return vectors; 574 } 575 576 static void * 577 gicv3_its_msi_intr_establish(struct arm_pci_msi *msi, 578 pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname) 579 { 580 struct gicv3_its * const its = msi->msi_priv; 581 const struct pci_attach_args *pa; 582 void *intrh; 583 584 const int lpi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 585 const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0; 586 587 intrh = pic_establish_intr(its->its_pic, lpi - its->its_pic->pic_irqbase, ipl, 588 IST_EDGE | mpsafe, func, arg, xname); 589 if (intrh == NULL) 590 return NULL; 591 592 /* Invalidate LPI configuration tables */ 593 pa = its->its_pa[lpi - its->its_pic->pic_irqbase]; 594 KASSERT(pa != NULL); 595 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 596 gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase); 597 598 return intrh; 599 } 600 601 static void 602 gicv3_its_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, 603 int count) 604 { 605 struct gicv3_its * const its = msi->msi_priv; 606 int n; 607 608 for (n = 0; n < count; n++) { 609 const int lpi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); 610 KASSERT(lpi >= its->its_pic->pic_irqbase); 611 if (pih[n] & ARM_PCI_INTR_MSIX) 612 gicv3_its_msix_disable(its, lpi); 613 if (pih[n] & ARM_PCI_INTR_MSI) 614 gicv3_its_msi_disable(its, lpi); 615 gicv3_its_msi_free_lpi(its, lpi); 616 its->its_targets[lpi - its->its_pic->pic_irqbase] = NULL; 617 struct intrsource * const is = 618 its->its_pic->pic_sources[lpi - its->its_pic->pic_irqbase]; 619 if (is != NULL) 620 pic_disestablish_source(is); 621 } 622 } 623 624 static void 625 gicv3_its_command_init(struct gicv3_softc *sc, struct gicv3_its *its) 626 { 627 uint64_t cbaser; 628 629 gicv3_dma_alloc(sc, &its->its_cmd, GITS_COMMANDS_SIZE, GITS_COMMANDS_ALIGN); 630 631 cbaser = its->its_cmd.segs[0].ds_addr; 632 cbaser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_CBASER_InnerCache); 633 cbaser |= __SHIFTIN(GITS_Shareability_NS, GITS_CBASER_Shareability); 634 cbaser |= __SHIFTIN((its->its_cmd.len / 4096) - 1, GITS_CBASER_Size); 635 cbaser |= GITS_CBASER_Valid; 636 637 gits_write_8(its, GITS_CBASER, cbaser); 638 gits_write_8(its, GITS_CWRITER, 0); 639 } 640 641 static void 642 gicv3_its_table_params(struct gicv3_softc *sc, struct gicv3_its *its, 643 u_int *devbits, u_int *innercache, u_int *share) 644 { 645 646 const uint64_t typer = gits_read_8(its, GITS_TYPER); 647 const uint32_t iidr = gits_read_4(its, GITS_IIDR); 648 649 /* Default values */ 650 *devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1; 651 *innercache = GITS_Cache_NORMAL_WA_WB; 652 *share = GITS_Shareability_IS; 653 654 /* Cavium ThunderX errata */ 655 if ((iidr & GITS_IIDR_CAVIUM_ERRATA_MASK) == GITS_IIDR_CAVIUM_ERRATA_VALUE) { 656 *devbits = 20; /* 8Mb */ 657 *innercache = GITS_Cache_DEVICE_nGnRnE; 658 aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n"); 659 } 660 } 661 662 static void 663 gicv3_its_table_init(struct gicv3_softc *sc, struct gicv3_its *its) 664 { 665 u_int table_size, page_size, table_align; 666 u_int devbits, innercache, share; 667 const char *table_type; 668 uint64_t baser; 669 int tab; 670 671 gicv3_its_table_params(sc, its, &devbits, &innercache, &share); 672 673 for (tab = 0; tab < 8; tab++) { 674 baser = gits_read_8(its, GITS_BASERn(tab)); 675 676 const u_int entry_size = __SHIFTOUT(baser, GITS_BASER_Entry_Size) + 1; 677 678 switch (__SHIFTOUT(baser, GITS_BASER_Page_Size)) { 679 case GITS_Page_Size_4KB: 680 page_size = 4096; 681 table_align = 4096; 682 break; 683 case GITS_Page_Size_16KB: 684 page_size = 16384; 685 table_align = 4096; 686 break; 687 case GITS_Page_Size_64KB: 688 default: 689 page_size = 65536; 690 table_align = 65536; 691 break; 692 } 693 694 switch (__SHIFTOUT(baser, GITS_BASER_Type)) { 695 case GITS_Type_Devices: 696 /* 697 * Table size scales with the width of the DeviceID. 698 */ 699 table_size = roundup(entry_size * (1 << devbits), page_size); 700 table_type = "Devices"; 701 break; 702 case GITS_Type_InterruptCollections: 703 /* 704 * Allocate space for one interrupt collection per CPU. 705 */ 706 table_size = roundup(entry_size * MAXCPUS, page_size); 707 table_type = "Collections"; 708 break; 709 default: 710 table_size = 0; 711 break; 712 } 713 714 if (table_size == 0) 715 continue; 716 717 gicv3_dma_alloc(sc, &its->its_tab[tab], table_size, table_align); 718 719 baser &= ~GITS_BASER_Size; 720 baser |= __SHIFTIN(table_size / page_size - 1, GITS_BASER_Size); 721 baser &= ~GITS_BASER_Physical_Address; 722 baser |= its->its_tab[tab].segs[0].ds_addr; 723 baser &= ~GITS_BASER_InnerCache; 724 baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache); 725 baser &= ~GITS_BASER_Shareability; 726 baser |= __SHIFTIN(share, GITS_BASER_Shareability); 727 baser |= GITS_BASER_Valid; 728 729 gits_write_8(its, GITS_BASERn(tab), baser); 730 731 baser = gits_read_8(its, GITS_BASERn(tab)); 732 if (__SHIFTOUT(baser, GITS_BASER_Shareability) == GITS_Shareability_NS) { 733 baser &= ~GITS_BASER_InnerCache; 734 baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache); 735 736 gits_write_8(its, GITS_BASERn(tab), baser); 737 } 738 739 baser = gits_read_8(its, GITS_BASERn(tab)); 740 aprint_normal_dev(sc->sc_dev, "ITS [#%d] %s table @ %#lx/%#x, %s, %s\n", 741 tab, table_type, its->its_tab[tab].segs[0].ds_addr, table_size, 742 gits_cache_type[__SHIFTOUT(baser, GITS_BASER_InnerCache)], 743 gits_share_type[__SHIFTOUT(baser, GITS_BASER_Shareability)]); 744 } 745 } 746 747 static void 748 gicv3_its_enable(struct gicv3_softc *sc, struct gicv3_its *its) 749 { 750 uint32_t ctlr; 751 752 ctlr = gits_read_4(its, GITS_CTLR); 753 ctlr |= GITS_CTLR_Enabled; 754 gits_write_4(its, GITS_CTLR, ctlr); 755 } 756 757 static void 758 gicv3_its_cpu_init(void *priv, struct cpu_info *ci) 759 { 760 struct gicv3_its * const its = priv; 761 struct gicv3_softc * const sc = its->its_gic; 762 const struct pci_attach_args *pa; 763 uint64_t rdbase; 764 size_t irq; 765 766 const uint64_t typer = bus_space_read_8(sc->sc_bst, its->its_bsh, GITS_TYPER); 767 if (typer & GITS_TYPER_PTA) { 768 void *va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh_r[ci->ci_gic_redist]); 769 rdbase = vtophys((vaddr_t)va); 770 } else { 771 rdbase = (uint64_t)sc->sc_processor_id[cpu_index(ci)] << 16; 772 } 773 its->its_rdbase[cpu_index(ci)] = rdbase; 774 775 /* 776 * Map collection ID of this CPU's index to this CPU's redistributor. 777 */ 778 gits_command_mapc(its, cpu_index(ci), rdbase, true); 779 gits_command_invall(its, cpu_index(ci)); 780 gits_wait(its); 781 782 /* 783 * Update routing for LPIs targetting this CPU 784 */ 785 for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) { 786 if (its->its_targets[irq] != ci) 787 continue; 788 pa = its->its_pa[irq]; 789 KASSERT(pa != NULL); 790 791 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 792 gits_command_movi(its, devid, irq, cpu_index(ci)); 793 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 794 } 795 796 its->its_cpuonline[cpu_index(ci)] = true; 797 } 798 799 static void 800 gicv3_its_get_affinity(void *priv, size_t irq, kcpuset_t *affinity) 801 { 802 struct gicv3_its * const its = priv; 803 struct cpu_info *ci; 804 805 kcpuset_zero(affinity); 806 ci = its->its_targets[irq]; 807 if (ci) 808 kcpuset_set(affinity, cpu_index(ci)); 809 } 810 811 static int 812 gicv3_its_set_affinity(void *priv, size_t irq, const kcpuset_t *affinity) 813 { 814 struct gicv3_its * const its = priv; 815 const struct pci_attach_args *pa; 816 struct cpu_info *ci; 817 818 const int set = kcpuset_countset(affinity); 819 if (set != 1) 820 return EINVAL; 821 822 pa = its->its_pa[irq]; 823 if (pa == NULL) 824 return EINVAL; 825 826 ci = cpu_lookup(kcpuset_ffs(affinity) - 1); 827 its->its_targets[irq] = ci; 828 829 if (its->its_cpuonline[cpu_index(ci)] == true) { 830 const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag); 831 gits_command_movi(its, devid, irq, cpu_index(ci)); 832 gits_command_sync(its, its->its_rdbase[cpu_index(ci)]); 833 } 834 835 return 0; 836 } 837 838 int 839 gicv3_its_init(struct gicv3_softc *sc, bus_space_handle_t bsh, 840 uint64_t its_base, uint32_t its_id) 841 { 842 struct gicv3_its *its; 843 struct arm_pci_msi *msi; 844 845 const uint64_t typer = bus_space_read_8(sc->sc_bst, bsh, GITS_TYPER); 846 if ((typer & GITS_TYPER_Physical) == 0) 847 return ENXIO; 848 849 its = kmem_alloc(sizeof(*its), KM_SLEEP); 850 its->its_id = its_id; 851 its->its_bst = sc->sc_bst; 852 its->its_bsh = bsh; 853 its->its_dmat = sc->sc_dmat; 854 its->its_base = its_base; 855 its->its_pic = &sc->sc_lpi; 856 snprintf(its->its_pic->pic_name, sizeof(its->its_pic->pic_name), "gicv3-its"); 857 KASSERT(its->its_pic->pic_maxsources > 0); 858 its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP); 859 its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP); 860 its->its_gic = sc; 861 its->its_cb.cpu_init = gicv3_its_cpu_init; 862 its->its_cb.get_affinity = gicv3_its_get_affinity; 863 its->its_cb.set_affinity = gicv3_its_set_affinity; 864 its->its_cb.priv = its; 865 LIST_INIT(&its->its_devices); 866 LIST_INSERT_HEAD(&sc->sc_lpi_callbacks, &its->its_cb, list); 867 868 gicv3_its_command_init(sc, its); 869 gicv3_its_table_init(sc, its); 870 871 gicv3_its_enable(sc, its); 872 873 gicv3_its_cpu_init(its, curcpu()); 874 875 msi = &its->its_msi; 876 msi->msi_dev = sc->sc_dev; 877 msi->msi_priv = its; 878 msi->msi_alloc = gicv3_its_msi_alloc; 879 msi->msix_alloc = gicv3_its_msix_alloc; 880 msi->msi_intr_establish = gicv3_its_msi_intr_establish; 881 msi->msi_intr_release = gicv3_its_msi_intr_release; 882 883 return arm_pci_msi_add(msi); 884 } 885