1ad28138bSmatt /*-
2ad28138bSmatt * Copyright (c) 2012 The NetBSD Foundation, Inc.
3ad28138bSmatt * All rights reserved.
4ad28138bSmatt *
5ad28138bSmatt * This code is derived from software contributed to The NetBSD Foundation
6ad28138bSmatt * by Matt Thomas of 3am Software Foundry.
7ad28138bSmatt *
8ad28138bSmatt * Redistribution and use in source and binary forms, with or without
9ad28138bSmatt * modification, are permitted provided that the following conditions
10ad28138bSmatt * are met:
11ad28138bSmatt * 1. Redistributions of source code must retain the above copyright
12ad28138bSmatt * notice, this list of conditions and the following disclaimer.
13ad28138bSmatt * 2. Redistributions in binary form must reproduce the above copyright
14ad28138bSmatt * notice, this list of conditions and the following disclaimer in the
15ad28138bSmatt * documentation and/or other materials provided with the distribution.
16ad28138bSmatt *
17ad28138bSmatt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18ad28138bSmatt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19ad28138bSmatt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20ad28138bSmatt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21ad28138bSmatt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22ad28138bSmatt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23ad28138bSmatt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24ad28138bSmatt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25ad28138bSmatt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ad28138bSmatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27ad28138bSmatt * POSSIBILITY OF SUCH DAMAGE.
28ad28138bSmatt */
29ad28138bSmatt
30ad28138bSmatt #include "opt_broadcom.h"
31ad28138bSmatt #include "locators.h"
32ad28138bSmatt #include "com.h"
33ad28138bSmatt #include "gpio.h"
34ad28138bSmatt #include "bcmcca.h"
35ad28138bSmatt
36ad28138bSmatt #define CCA_PRIVATE
37ad28138bSmatt #define CRU_PRIVATE
38ad28138bSmatt #define IDM_PRIVATE
39ad28138bSmatt
40ad28138bSmatt #if NCOM == 0
41ad28138bSmatt #error no console configured
42ad28138bSmatt #endif
43ad28138bSmatt
44ad28138bSmatt #include <sys/cdefs.h>
45ad28138bSmatt
46*14ad16f0Sskrll __KERNEL_RCSID(1, "$NetBSD: bcm53xx_cca.c,v 1.6 2024/02/16 15:11:17 skrll Exp $");
47ad28138bSmatt
48ad28138bSmatt #include <sys/param.h>
49ad28138bSmatt #include <sys/bus.h>
50ad28138bSmatt #include <sys/device.h>
51ad28138bSmatt #include <sys/intr.h>
52ad28138bSmatt #include <sys/systm.h>
53ad28138bSmatt #include <sys/time.h>
54ad28138bSmatt #include <sys/termios.h>
55ad28138bSmatt
56ad28138bSmatt #include <dev/ic/comreg.h>
57ad28138bSmatt #include <dev/ic/comvar.h>
58ad28138bSmatt
59ad28138bSmatt #include <arm/mainbus/mainbus.h>
60ad28138bSmatt
61ad28138bSmatt #include <arm/broadcom/bcm53xx_reg.h>
62ad28138bSmatt #include <arm/broadcom/bcm53xx_var.h>
63ad28138bSmatt
64ad28138bSmatt static int bcmcca_mainbus_match(device_t, cfdata_t, void *);
65ad28138bSmatt static void bcmcca_mainbus_attach(device_t, device_t, void *);
66ad28138bSmatt
67ad28138bSmatt struct bcmcca_softc;
68ad28138bSmatt static void bcmcca_uart_attach(struct bcmcca_softc *sc);
69ad28138bSmatt #if NGPIO > 0
70ad28138bSmatt static void bcmcca_gpio_attach(struct bcmcca_softc *sc);
71ad28138bSmatt #endif
72ad28138bSmatt
73ad28138bSmatt struct bcmcca_softc {
74ad28138bSmatt device_t sc_dev;
75ad28138bSmatt bus_space_tag_t sc_bst;
76ad28138bSmatt bus_space_handle_t sc_bsh;
77ad28138bSmatt struct com_softc *sc_com_softc[2];
78ad28138bSmatt void *sc_ih;
79ad28138bSmatt uint32_t sc_gpiopins;
80ad28138bSmatt };
81ad28138bSmatt
82ad28138bSmatt struct bcmcca_attach_args {
83ad28138bSmatt bus_space_tag_t ccaaa_bst;
84ad28138bSmatt bus_space_handle_t ccaaa_bsh;
85ad28138bSmatt bus_size_t ccaaa_offset;
86ad28138bSmatt bus_size_t ccaaa_size;
87ad28138bSmatt int ccaaa_channel;
88ad28138bSmatt };
89ad28138bSmatt
90ad28138bSmatt static struct bcmcca_softc bcmcca_sc = {
91ad28138bSmatt .sc_gpiopins = 0xffffff, /* assume all 24 pins are available */
92ad28138bSmatt };
93ad28138bSmatt
94ad28138bSmatt CFATTACH_DECL_NEW(bcmcca, 0,
95ad28138bSmatt bcmcca_mainbus_match, bcmcca_mainbus_attach, NULL, NULL);
96ad28138bSmatt
97ad28138bSmatt static int
bcmcca_mainbus_match(device_t parent,cfdata_t cf,void * aux)98ad28138bSmatt bcmcca_mainbus_match(device_t parent, cfdata_t cf, void *aux)
99ad28138bSmatt {
100ad28138bSmatt if (bcmcca_sc.sc_dev != NULL)
101ad28138bSmatt return 0;
102ad28138bSmatt
103ad28138bSmatt return 1;
104ad28138bSmatt }
105ad28138bSmatt
106ad28138bSmatt static int
bcmcca_print(void * aux,const char * pnp)107ad28138bSmatt bcmcca_print(void *aux, const char *pnp)
108ad28138bSmatt {
109ad28138bSmatt const struct bcmcca_attach_args * const ccaaa = aux;
110ad28138bSmatt
111ad28138bSmatt if (ccaaa->ccaaa_channel != BCMCCACF_CHANNEL_DEFAULT)
112ad28138bSmatt aprint_normal(" channel %d", ccaaa->ccaaa_channel);
113ad28138bSmatt
114ad28138bSmatt return QUIET;
115ad28138bSmatt }
116ad28138bSmatt
117ad28138bSmatt static inline uint32_t
bcmcca_read_4(struct bcmcca_softc * sc,bus_size_t o)118ad28138bSmatt bcmcca_read_4(struct bcmcca_softc *sc, bus_size_t o)
119ad28138bSmatt {
120ad28138bSmatt return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o);
121ad28138bSmatt }
122ad28138bSmatt
123ad28138bSmatt static inline void
bcmcca_write_4(struct bcmcca_softc * sc,bus_size_t o,uint32_t v)124ad28138bSmatt bcmcca_write_4(struct bcmcca_softc *sc, bus_size_t o, uint32_t v)
125ad28138bSmatt {
126ad28138bSmatt return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v);
127ad28138bSmatt }
128ad28138bSmatt
129ad28138bSmatt static int
bcmcca_intr(void * arg)130ad28138bSmatt bcmcca_intr(void *arg)
131ad28138bSmatt {
132ad28138bSmatt struct bcmcca_softc * sc = arg;
133ad28138bSmatt int rv = 0;
134ad28138bSmatt
135ad28138bSmatt uint32_t v = bcmcca_read_4(sc, MISC_INTSTATUS);
136ad28138bSmatt if (v & INTSTATUS_UARTINT) {
137ad28138bSmatt if (sc->sc_com_softc[0] != NULL)
138ad28138bSmatt rv = comintr(sc->sc_com_softc[0]);
139ad28138bSmatt if (sc->sc_com_softc[1] != NULL) {
140ad28138bSmatt int rv0 = comintr(sc->sc_com_softc[1]);
141ad28138bSmatt if (rv)
142ad28138bSmatt rv = rv0;
143ad28138bSmatt }
144ad28138bSmatt }
145ad28138bSmatt if (v & INTSTATUS_GPIOINT) {
146ad28138bSmatt
147ad28138bSmatt }
148ad28138bSmatt return rv;
149ad28138bSmatt }
150ad28138bSmatt
151ad28138bSmatt static void
bcmcca_mainbus_attach(device_t parent,device_t self,void * aux)152ad28138bSmatt bcmcca_mainbus_attach(device_t parent, device_t self, void *aux)
153ad28138bSmatt {
154ad28138bSmatt struct bcmcca_softc * const sc = &bcmcca_sc;
155ad28138bSmatt
156ad28138bSmatt sc->sc_dev = self;
1572e6fd77aSriastradh device_set_private(self, sc);
158ad28138bSmatt
159ad28138bSmatt sc->sc_bst = bcm53xx_ioreg_bst;
160ad28138bSmatt
161ad28138bSmatt bus_space_subregion (sc->sc_bst, bcm53xx_ioreg_bsh,
162ad28138bSmatt CCA_MISC_BASE, CCA_MISC_SIZE, &sc->sc_bsh);
163ad28138bSmatt
164ad28138bSmatt uint32_t chipid = bcmcca_read_4(sc, MISC_CHIPID);
165ad28138bSmatt
166ad28138bSmatt aprint_naive("\n");
167ad28138bSmatt aprint_normal(": BCM%u (Rev %c%u)\n",
168ad28138bSmatt (u_int)__SHIFTOUT(chipid, CHIPID_ID),
169ad28138bSmatt (u_int)('A' + (__SHIFTOUT(chipid, CHIPID_REV) >> 2)),
170ad28138bSmatt (u_int)(__SHIFTOUT(chipid, CHIPID_REV) & 3));
171ad28138bSmatt
172ad28138bSmatt sc->sc_ih = intr_establish(IRQ_CCA, IPL_TTY, IST_LEVEL, bcmcca_intr, sc);
173ad28138bSmatt if (sc->sc_ih == NULL) {
174ad28138bSmatt aprint_error_dev(sc->sc_dev, "failed to establish CCA intr\n");
175ad28138bSmatt return;
176ad28138bSmatt }
177ad28138bSmatt aprint_normal_dev(sc->sc_dev, "interrupting at irq %d\n", IRQ_CCA);
178ad28138bSmatt
179ad28138bSmatt bcmcca_uart_attach(sc);
180ad28138bSmatt #if NGPIO > 0
181ad28138bSmatt bcmcca_gpio_attach(sc);
182ad28138bSmatt #endif
183ad28138bSmatt }
184ad28138bSmatt
185ad28138bSmatt static void
bcmcca_uart_attach(struct bcmcca_softc * sc)186ad28138bSmatt bcmcca_uart_attach(struct bcmcca_softc *sc)
187ad28138bSmatt {
188ad28138bSmatt struct bcmcca_attach_args ccaaa = {
189ad28138bSmatt .ccaaa_bst = sc->sc_bst,
190ad28138bSmatt .ccaaa_bsh = sc->sc_bsh,
191ad28138bSmatt .ccaaa_offset = CCA_UART0_BASE,
192ad28138bSmatt .ccaaa_size = COM_NPORTS,
193ad28138bSmatt .ccaaa_channel = 0,
194ad28138bSmatt };
195ad28138bSmatt device_t dv;
196ad28138bSmatt
197ad28138bSmatt #if 0
198ad28138bSmatt /*
199ad28138bSmatt * Force the UART to use the BCM53xx reference clock.
200ad28138bSmatt */
201ad28138bSmatt uint32_t v = bcmcca_read_4(sc, IDM_BASE + APBX_IDM_IO_CONTROL_DIRECT);
202ad28138bSmatt if (v & IO_CONTROL_DIRECT_UARTCLKSEL) {
203ad28138bSmatt v &= ~IO_CONTROL_DIRECT_UARTCLKSEL;
204ad28138bSmatt bcmcca_write_4(sc, IDM_BASE + APBX_IDM_IO_CONTROL_DIRECT, v);
205ad28138bSmatt }
206ad28138bSmatt v = bcmcca_read_4(sc, MISC_CORECTL);
207ad28138bSmatt if (v & CORECTL_UART_CLK_OVERRIDE) {
208ad28138bSmatt v &= ~CORECTL_UART_CLK_OVERRIDE;
209ad28138bSmatt bcmcca_write_4(sc, MISC_CORECTL, v);
210ad28138bSmatt }
211ad28138bSmatt #endif
212ad28138bSmatt
213ad28138bSmatt bool children = false;
214ad28138bSmatt
215c7fb772bSthorpej dv = config_found(sc->sc_dev, &ccaaa, bcmcca_print, CFARGS_NONE);
216ad28138bSmatt if (dv != NULL) {
217ad28138bSmatt sc->sc_com_softc[0] = device_private(dv);
218ad28138bSmatt children = true;
219ad28138bSmatt }
220ad28138bSmatt
221ad28138bSmatt ccaaa.ccaaa_offset = CCA_UART1_BASE;
222ad28138bSmatt ccaaa.ccaaa_channel = 1;
223ad28138bSmatt
224c7fb772bSthorpej dv = config_found(sc->sc_dev, &ccaaa, bcmcca_print, CFARGS_NONE);
225ad28138bSmatt if (dv != NULL) {
226ad28138bSmatt sc->sc_com_softc[1] = device_private(dv);
227ad28138bSmatt children = true;
228ad28138bSmatt /*
229ad28138bSmatt * UART1 uses the same pins as GPIO pins 15..12
230ad28138bSmatt */
231ad28138bSmatt sc->sc_gpiopins &= ~__BITS(15,12);
232ad28138bSmatt }
233ad28138bSmatt
234ad28138bSmatt if (children) {
235ad28138bSmatt /*
236ad28138bSmatt * If we configured children, enable interrupts for the UART(s).
237ad28138bSmatt */
238ad28138bSmatt uint32_t intmask = bcmcca_read_4(sc, MISC_INTMASK);
239ad28138bSmatt intmask |= INTMASK_UARTINT;
240ad28138bSmatt bcmcca_write_4(sc, MISC_INTMASK, intmask);
241ad28138bSmatt }
242ad28138bSmatt }
243ad28138bSmatt
244ad28138bSmatt static int com_cca_match(device_t, cfdata_t, void *);
245ad28138bSmatt static void com_cca_attach(device_t, device_t, void *);
246ad28138bSmatt
247ad28138bSmatt CFATTACH_DECL_NEW(com_cca, sizeof(struct com_softc),
248ad28138bSmatt com_cca_match, com_cca_attach, NULL, NULL);
249ad28138bSmatt
250ad28138bSmatt static int
com_cca_match(device_t parent,cfdata_t cf,void * aux)251ad28138bSmatt com_cca_match(device_t parent, cfdata_t cf, void *aux)
252ad28138bSmatt {
253ad28138bSmatt struct bcmcca_attach_args * const ccaaa = aux;
254ad28138bSmatt const int channel = cf->cf_loc[BCMCCACF_CHANNEL];
255ad28138bSmatt const bus_addr_t addr = BCM53XX_IOREG_PBASE + ccaaa->ccaaa_offset;
256ad28138bSmatt bus_space_handle_t bsh;
257ad28138bSmatt
258ad28138bSmatt KASSERT(ccaaa->ccaaa_offset == CCA_UART0_BASE || ccaaa->ccaaa_offset == CCA_UART1_BASE);
259ad28138bSmatt KASSERT(bcmcca_sc.sc_com_softc[ccaaa->ccaaa_channel] == NULL);
260ad28138bSmatt
261ad28138bSmatt if (channel != BCMCCACF_CHANNEL_DEFAULT && channel != ccaaa->ccaaa_channel)
262ad28138bSmatt return 0;
263ad28138bSmatt
264ad28138bSmatt if (com_is_console(ccaaa->ccaaa_bst, addr, NULL))
265ad28138bSmatt return 1;
266ad28138bSmatt
267ad28138bSmatt bus_space_subregion(ccaaa->ccaaa_bst, ccaaa->ccaaa_bsh,
268ad28138bSmatt ccaaa->ccaaa_offset, ccaaa->ccaaa_size, &bsh);
269ad28138bSmatt
270ad28138bSmatt return comprobe1(ccaaa->ccaaa_bst, bsh);
271ad28138bSmatt }
272ad28138bSmatt
273ad28138bSmatt static void
com_cca_attach(device_t parent,device_t self,void * aux)274ad28138bSmatt com_cca_attach(device_t parent, device_t self, void *aux)
275ad28138bSmatt {
276ad28138bSmatt struct com_softc * const sc = device_private(self);
277ad28138bSmatt struct bcmcca_attach_args * const ccaaa = aux;
278ad28138bSmatt const bus_addr_t addr = BCM53XX_IOREG_PBASE + ccaaa->ccaaa_offset;
279ad28138bSmatt bus_space_handle_t bsh;
280ad28138bSmatt
281ad28138bSmatt sc->sc_dev = self;
282ad28138bSmatt sc->sc_frequency = BCM53XX_REF_CLK;
283ad28138bSmatt sc->sc_type = COM_TYPE_NORMAL;
284ad28138bSmatt
285ad28138bSmatt if (com_is_console(ccaaa->ccaaa_bst, addr, &bsh) == 0 &&
286ad28138bSmatt bus_space_subregion(ccaaa->ccaaa_bst, ccaaa->ccaaa_bsh,
287ad28138bSmatt ccaaa->ccaaa_offset, ccaaa->ccaaa_size, &bsh)) {
288ad28138bSmatt panic(": can't map registers\n");
289ad28138bSmatt return;
290ad28138bSmatt }
2916d487047Sthorpej com_init_regs(&sc->sc_regs, ccaaa->ccaaa_bst, bsh, addr);
292ad28138bSmatt
293ad28138bSmatt com_attach_subr(sc);
294ad28138bSmatt }
295ad28138bSmatt
296ad28138bSmatt #if NGPIO > 0
297ad28138bSmatt static void
bcmcca_gpio_attach(struct bcmcca_softc * sc)298ad28138bSmatt bcmcca_gpio_attach(struct bcmcca_softc *sc)
299ad28138bSmatt {
300ad28138bSmatt /*
301ad28138bSmatt * First see if there are any pins being used as GPIO pins...
302ad28138bSmatt */
303ad28138bSmatt uint32_t v = bcmcca_read(sc, CRU_BASE + CRU_GPIO_SELECT);
304ad28138bSmatt if (v == 0)
305ad28138bSmatt return;
306ad28138bSmatt }
307ad28138bSmatt #endif
308