1*cff5caddSsnj /* $Id: at91tcreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 2*cff5caddSsnj /* $NetBSD: at91tcreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 3c62a0ac4Smatt 4c62a0ac4Smatt /*- 5c62a0ac4Smatt * Copyright (c) 2007 Embedtronics Oy 6c62a0ac4Smatt * 7c62a0ac4Smatt * Redistribution and use in source and binary forms, with or without 8c62a0ac4Smatt * modification, are permitted provided that the following conditions 9c62a0ac4Smatt * are met: 10c62a0ac4Smatt * 1. Redistributions of source code must retain the above copyright 11c62a0ac4Smatt * notice, this list of conditions and the following disclaimer. 12c62a0ac4Smatt * 2. Redistributions in binary form must reproduce the above copyright 13c62a0ac4Smatt * notice, this list of conditions and the following disclaimer in the 14c62a0ac4Smatt * documentation and/or other materials provided with the distribution. 15*cff5caddSsnj * 16c62a0ac4Smatt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17c62a0ac4Smatt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18c62a0ac4Smatt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19c62a0ac4Smatt * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20c62a0ac4Smatt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21c62a0ac4Smatt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22c62a0ac4Smatt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23c62a0ac4Smatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24c62a0ac4Smatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25c62a0ac4Smatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26c62a0ac4Smatt * SUCH DAMAGE. 27c62a0ac4Smatt * 28c62a0ac4Smatt */ 29c62a0ac4Smatt 30c62a0ac4Smatt #ifndef _AT91TCREG_H_ 31c62a0ac4Smatt #define _AT91TCREG_H_ 1 32c62a0ac4Smatt 33c62a0ac4Smatt /* Timer Counter (TC), 34c62a0ac4Smatt * at91rm9200.pdf, Page 485 */ 35c62a0ac4Smatt 36c62a0ac4Smatt /* channel registers: */ 37c62a0ac4Smatt #define TCC_COUNT 3 38c62a0ac4Smatt 39c62a0ac4Smatt #define TC_CCR 0x00U /* 0x00: Channel Control Register */ 40c62a0ac4Smatt #define TC_CMR 0x04U /* 0x04: Channel Mode Register */ 41c62a0ac4Smatt #define TC_CV 0x10U /* 0x10: Counter Value */ 42c62a0ac4Smatt #define TC_RA 0x14U /* 0x14: Register A */ 43c62a0ac4Smatt #define TC_RB 0x18U /* 0x18: Register B */ 44c62a0ac4Smatt #define TC_RC 0x1CU /* 0x1C: Register C */ 45c62a0ac4Smatt #define TC_SR 0x20U /* 0x20: Status Register */ 46c62a0ac4Smatt #define TC_IER 0x24U /* 0x24: Interrupt Enable Register */ 47c62a0ac4Smatt #define TC_IDR 0x28U /* 0x28: Interrupt Disable Register */ 48c62a0ac4Smatt #define TC_IMR 0x2CU /* 0x2C: Interrupt Mask Register */ 49c62a0ac4Smatt 50c62a0ac4Smatt /* Channel Control Register bits: */ 51c62a0ac4Smatt #define TC_CCR_SWTRG 0x00000004U /* 1 = software trigger command */ 52c62a0ac4Smatt #define TC_CCR_CLKDIS 0x00000002U /* 1 = disable clock */ 53c62a0ac4Smatt #define TC_CCR_CLKEN 0x00000001U /* 1 = enable clock */ 54c62a0ac4Smatt 55c62a0ac4Smatt 56c62a0ac4Smatt /* Channel Mode Register bits in both modes : */ 57c62a0ac4Smatt #define TC_CMR_WAVE 0x00008000U /* 1 = waveform mode (not capture) */ 58c62a0ac4Smatt 59c62a0ac4Smatt #define TC_CMR_BURST 0x00000030U /* burst signal selection */ 60c62a0ac4Smatt #define TC_CMR_BURST_SHIFT 4U 61c62a0ac4Smatt #define TC_CMR_BURST_NONE 0x00000000U 62c62a0ac4Smatt #define TC_CMR_BURST_XC0 0x00000010U 63c62a0ac4Smatt #define TC_CMR_BURST_XC1 0x00000020U 64c62a0ac4Smatt #define TC_CMR_BURST_XC2 0x00000030U 65c62a0ac4Smatt 66c62a0ac4Smatt #define TC_CMR_CLKI 0x00000008U /* 1 = increment on falling edge */ 67c62a0ac4Smatt 68c62a0ac4Smatt #define TC_CMR_TCCLKS 0x00000007U /* clock selection */ 69c62a0ac4Smatt #define TC_CMR_TCCLKS_SHIFT 0U 70c62a0ac4Smatt #define TC_CMR_TCCLKS_CLOCK1 0x00000000U 71c62a0ac4Smatt #define TC_CMR_TCCLKS_CLOCK2 0x00000001U 72c62a0ac4Smatt #define TC_CMR_TCCLKS_CLOCK3 0x00000002U 73c62a0ac4Smatt #define TC_CMR_TCCLKS_CLOCK4 0x00000003U 74c62a0ac4Smatt #define TC_CMR_TCCLKS_CLOCK5 0x00000004U 75c62a0ac4Smatt #define TC_CMR_TCCLKS_XC0 0x00000005U 76c62a0ac4Smatt #define TC_CMR_TCCLKS_XC1 0x00000006U 77c62a0ac4Smatt #define TC_CMR_TCCLKS_XC2 0x00000007U 78c62a0ac4Smatt #define TC_CMR_TCCLKS_MCK_DIV_2 TC_CMR_TCCLKS_CLOCK1 79c62a0ac4Smatt #define TC_CMR_TCCLKS_MCK_DIV_8 TC_CMR_TCCLKS_CLOCK2 80c62a0ac4Smatt #define TC_CMR_TCCLKS_MCK_DIV_32 TC_CMR_TCCLKS_CLOCK3 81c62a0ac4Smatt #define TC_CMR_TCCLKS_MCK_DIV_128 TC_CMR_TCCLKS_CLOCK4 82c62a0ac4Smatt #define TC_CMR_TCCLKS_SLCK TC_CMR_TCCLKS_CLOCK5 83c62a0ac4Smatt 84c62a0ac4Smatt 85c62a0ac4Smatt /* Channel Mode Register bits in capture mode: */ 86c62a0ac4Smatt #define TC_CMR_LDRB 0x000C0000U 87c62a0ac4Smatt #define TC_CMR_LDRB_SHIFT 18U 88c62a0ac4Smatt #define TC_CMR_LDRB_NONE 0x00000000U 89c62a0ac4Smatt #define TC_CMR_LDRB_RISING 0x00040000U 90c62a0ac4Smatt #define TC_CMR_LDRB_FALLING 0x00080000U 91c62a0ac4Smatt #define TC_CMR_LDRB_BOTH 0x000C0000U 92c62a0ac4Smatt 93c62a0ac4Smatt #define TC_CMR_LDRA 0x00030000U 94c62a0ac4Smatt #define TC_CMR_LDRA_SHIFT 16U 95c62a0ac4Smatt #define TC_CMR_LDRA_NONE 0x00000000U 96c62a0ac4Smatt #define TC_CMR_LDRA_RISING 0x00010000U 97c62a0ac4Smatt #define TC_CMR_LDRA_FALLING 0x00020000U 98c62a0ac4Smatt #define TC_CMR_LDRA_BOTH 0x00030000U 99c62a0ac4Smatt 100c62a0ac4Smatt 101c62a0ac4Smatt #define TC_CMR_CPCTRG 0x00004000U /* 1 = RC compare resets cntr */ 102c62a0ac4Smatt #define TC_CMR_ABETRG 0x00000400U /* 1 = TIOA is ext trig */ 103c62a0ac4Smatt 104c62a0ac4Smatt #define TC_CMR_ETRGEDG 0x00000300U /* external trigger edge sel */ 105c62a0ac4Smatt #define TC_CMR_ETRGEDG_SHIFT 8U 106c62a0ac4Smatt #define TC_CMR_ETRGEDG_NONE 0x00000000U 107c62a0ac4Smatt #define TC_CMR_ETRGEDG_RISING 0x00000100U 108c62a0ac4Smatt #define TC_CMR_ETRGEDG_FALLING 0x00000200U 109c62a0ac4Smatt #define TC_CMR_ETRGEDG_BOTH 0x00000300U 110c62a0ac4Smatt 111c62a0ac4Smatt #define TC_CMR_LDBDIS 0x00000080U /* 1 = disable counter after loading RB */ 112c62a0ac4Smatt #define TC_CMR_LDBSTOP 0x00000040U /* 1 = stop counter after loading RB */ 113c62a0ac4Smatt 114c62a0ac4Smatt /* Channel Mode Register bits in Waveform mode: */ 115c62a0ac4Smatt #define TC_CMR_BSWTRG 0xC0000000U /* Software Trigger Effect on TIOB */ 116c62a0ac4Smatt #define TC_CMR_BSWTRG_NONE 0x00000000U 117c62a0ac4Smatt #define TC_CMR_BSWTRG_SET 0x40000000U 118c62a0ac4Smatt #define TC_CMR_BSWTRG_CLEAR 0x80000000U 119c62a0ac4Smatt #define TC_CMR_BSWTRG_TOGGLE 0xC0000000U 120c62a0ac4Smatt 121c62a0ac4Smatt #define TC_CMR_BEEVT 0x30000000U /* External Event Effect on TIOB */ 122c62a0ac4Smatt #define TC_CMR_BEEVT_NONE 0x00000000U 123c62a0ac4Smatt #define TC_CMR_BEEVT_SET 0x10000000U 124c62a0ac4Smatt #define TC_CMR_BEEVT_CLEAR 0x20000000U 125c62a0ac4Smatt #define TC_CMR_BEEVT_TOGGLE 0x30000000U 126c62a0ac4Smatt 127c62a0ac4Smatt #define TC_CMR_BCPC 0x0C000000U /* RC Compare Effect on TIOB */ 128c62a0ac4Smatt #define TC_CMR_BCPC_NONE 0x00000000U 129c62a0ac4Smatt #define TC_CMR_BCPC_SET 0x04000000U 130c62a0ac4Smatt #define TC_CMR_BCPC_CLEAR 0x08000000U 131c62a0ac4Smatt #define TC_CMR_BCPC_TOGGLE 0x0C000000U 132c62a0ac4Smatt 133c62a0ac4Smatt #define TC_CMR_BCPB 0x03000000U /* RB Compare Effect on TIOB */ 134c62a0ac4Smatt #define TC_CMR_BCPB_NONE 0x00000000U 135c62a0ac4Smatt #define TC_CMR_BCPB_SET 0x01000000U 136c62a0ac4Smatt #define TC_CMR_BCPB_CLEAR 0x02000000U 137c62a0ac4Smatt #define TC_CMR_BCPB_TOGGLE 0x03000000U 138c62a0ac4Smatt 139c62a0ac4Smatt #define TC_CMR_ASWTRG 0x00C00000U /* Software Trigger Effect on TIOA: */ 140c62a0ac4Smatt #define TC_CMR_ASWTRG_NONE 0x00000000U 141c62a0ac4Smatt #define TC_CMR_ASWTRG_SET 0x00400000U 142c62a0ac4Smatt #define TC_CMR_ASWTRG_CLEAR 0x00800000U 143c62a0ac4Smatt #define TC_CMR_ASWTRG_TOGGLE 0x00C00000U 144c62a0ac4Smatt 145c62a0ac4Smatt #define TC_CMR_AEVT 0x00300000U 146c62a0ac4Smatt #define TC_CMR_AEVT_NONE 0x00000000U 147c62a0ac4Smatt #define TC_CMR_AEVT_SET 0x00100000U 148c62a0ac4Smatt #define TC_CMR_AEVT_CLEAR 0x00200000U 149c62a0ac4Smatt #define TC_CMR_AEVT_TOGGLE 0x00300000U 150c62a0ac4Smatt 151c62a0ac4Smatt #define TC_CMR_ACPC 0x000C0000U /* RC Compare Effect on TIOA: */ 152c62a0ac4Smatt #define TC_CMR_ACPC_NONE 0x00000000U 153c62a0ac4Smatt #define TC_CMR_ACPC_SET 0x00040000U 154c62a0ac4Smatt #define TC_CMR_ACPC_CLEAR 0x00080000U 155c62a0ac4Smatt #define TC_CMR_ACPC_TOGGLE 0x000C0000U 156c62a0ac4Smatt 157c62a0ac4Smatt #define TC_CMR_ACPA 0x00030000U /* RA Compare Effect on TIOA: */ 158c62a0ac4Smatt #define TC_CMR_ACPA_NONE 0x00000000U 159c62a0ac4Smatt #define TC_CMR_ACPA_SET 0x00010000U 160c62a0ac4Smatt #define TC_CMR_ACPA_CLEAR 0x00020000U 161c62a0ac4Smatt #define TC_CMR_ACPA_TOGGLE 0x00030000U 162c62a0ac4Smatt 163c62a0ac4Smatt #define TC_CMR_WAVSEL 0x00006000U /* Waveform selection */ 164c62a0ac4Smatt #define TC_CMR_WAVSEL_UP 0x00000000U 165c62a0ac4Smatt #define TC_CMR_WAVSEL_UPDOWN 0x00002000U 166c62a0ac4Smatt #define TC_CMR_WAVSEL_UP_RC 0x00004000U 167c62a0ac4Smatt #define TC_CMR_WAVSEL_UPDOWN_RC 0x00006000U 168c62a0ac4Smatt 169c62a0ac4Smatt #define TC_CMR_ENETRG 0x00001000U /* 1 = external event resets the cntr */ 170c62a0ac4Smatt 171c62a0ac4Smatt #define TC_CMR_EEVT 0x00000C00U /* External Event Sel */ 172c62a0ac4Smatt #define TC_CMR_EEVT_TIOB 0x00000000U 173c62a0ac4Smatt #define TC_CMR_EEVT_XC0 0x00000400U 174c62a0ac4Smatt #define TC_CMR_EEVT_XC1 0x00000800U 175c62a0ac4Smatt #define TC_CMR_EEVT_XC2 0x00000C00U 176c62a0ac4Smatt 177c62a0ac4Smatt 178c62a0ac4Smatt #define TC_CMR_EEVTEDG 0x00000300U /* External Event Edge Sel */ 179c62a0ac4Smatt #define TC_CMR_EEVTEDG_NONE 0x00000000U 180c62a0ac4Smatt #define TC_CMR_EEVTEDG_RISING 0x00000100U 181c62a0ac4Smatt #define TC_CMR_EEVTEDG_FALLING 0x00000200U 182c62a0ac4Smatt #define TC_CMR_EEVTEDG_BOTH 0x00000300U 183c62a0ac4Smatt 184c62a0ac4Smatt #define TC_CMR_CPCDIS 0x00000080U /* 1 = RC compare disables cntr */ 185c62a0ac4Smatt #define TC_CMR_CPCSTOP 0x00000040U /* 1 = RC compare stops cntr */ 186c62a0ac4Smatt 187c62a0ac4Smatt 188c62a0ac4Smatt /* Channel Status Register bits: */ 189c62a0ac4Smatt #define TC_SR_MTIOB 0x00040000U 190c62a0ac4Smatt #define TC_SR_MTIOA 0x00020000U 191c62a0ac4Smatt #define TC_SR_CLKSTA 0x00010000U 192c62a0ac4Smatt 193c62a0ac4Smatt #define TC_SR_ETRGS 0x80U 194c62a0ac4Smatt #define TC_SR_LDRBS 0x40U 195c62a0ac4Smatt #define TC_SR_LDRAS 0x20U 196c62a0ac4Smatt #define TC_SR_CPCS 0x10U 197c62a0ac4Smatt #define TC_SR_CPBS 0x08U 198c62a0ac4Smatt #define TC_SR_CPAS 0x04U 199c62a0ac4Smatt #define TC_SR_LOVRS 0x02U 200c62a0ac4Smatt #define TC_SR_COVFS 0x01U 201c62a0ac4Smatt 202c62a0ac4Smatt 203c62a0ac4Smatt /* timer registers: */ 204c62a0ac4Smatt 205c62a0ac4Smatt #define TC_BCR 0x00U /* Block Control Register */ 206c62a0ac4Smatt #define TC_BMR 0x04U /* Block Mode Register */ 207c62a0ac4Smatt 208c62a0ac4Smatt /* Block Control Register bits: */ 209c62a0ac4Smatt #define TC_BCR_SYNC 0x00000001U /* 1 = asserts the SYNC signal */ 210c62a0ac4Smatt 211c62a0ac4Smatt /* Block Mode Register bits: */ 212c62a0ac4Smatt #define TC_BMR_TC2XC2S 0x30U /* External Clock Signal 2 Sel */ 213c62a0ac4Smatt #define TC_BMR_TC2XC2S_SHIFT 4U 214c62a0ac4Smatt #define TC_BMR_TC2XC2S_TCLK2 0x00U 215c62a0ac4Smatt #define TC_BMR_TC2XC2S_TIOA0 0x20U 216c62a0ac4Smatt #define TC_BMR_TC2XC2S_TIOA1 0x30U 217c62a0ac4Smatt 218c62a0ac4Smatt #define TC_BMR_TC1XC1S 0x0CU /* External Clock Signal 1 Sel */ 219c62a0ac4Smatt #define TC_BMR_TC1XC1S_SHIFT 2U 220c62a0ac4Smatt #define TC_BMR_TC1XC1S_TCLK1 0x00U 221c62a0ac4Smatt #define TC_BMR_TC1XC1S_TIOA0 0x08U 222c62a0ac4Smatt #define TC_BMR_TC1XC1S_TIOA2 0x0CU 223c62a0ac4Smatt 224c62a0ac4Smatt #define TC_BMR_TC0XC0S 0x03U /* External Clock Signal 0 Sel */ 225c62a0ac4Smatt #define TC_BMR_TC0XC0S_SHIFT 0U 226c62a0ac4Smatt #define TC_BMR_TC0XC0S_TCLK0 0x00U 227c62a0ac4Smatt #define TC_BMR_TC0XC0S_TIOA1 0x02U 228c62a0ac4Smatt #define TC_BMR_TC0XC0S_TIOA2 0x03U 229c62a0ac4Smatt 230c62a0ac4Smatt #endif /* !_AT91TCREG_H_ */ 231