1*c62a0ac4Smatt /* $Id: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 2*c62a0ac4Smatt /* $NetBSD: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */ 3*c62a0ac4Smatt 4*c62a0ac4Smatt /*- 5*c62a0ac4Smatt * Copyright (c) 2007 Embedtronics Oy. 6*c62a0ac4Smatt * All rights reserved. 7*c62a0ac4Smatt * 8*c62a0ac4Smatt * Redistribution and use in source and binary forms, with or 9*c62a0ac4Smatt * without modification, are permitted provided that the following 10*c62a0ac4Smatt * conditions are met: 11*c62a0ac4Smatt * 1. Redistributions of source code must retain the above copyright 12*c62a0ac4Smatt * notice, this list of conditions and the following disclaimer. 13*c62a0ac4Smatt * 2. Redistributions in binary form must reproduce the above 14*c62a0ac4Smatt * copyright notice, this list of conditions and the following 15*c62a0ac4Smatt * disclaimer in the documentation and/or other materials provided 16*c62a0ac4Smatt * with the distribution. 17*c62a0ac4Smatt * 3. All advertising materials mentioning features or use of this 18*c62a0ac4Smatt * software must display the following acknowledgements: 19*c62a0ac4Smatt * This product includes software developed by the Urbana-Champaign 20*c62a0ac4Smatt * Independent Media Center. 21*c62a0ac4Smatt * This product includes software developed by Garrett D'Amore. 22*c62a0ac4Smatt * 4. Urbana-Champaign Independent Media Center's name and Garrett 23*c62a0ac4Smatt * D'Amore's name may not be used to endorse or promote products 24*c62a0ac4Smatt * derived from this software without specific prior written permission. 25*c62a0ac4Smatt * 26*c62a0ac4Smatt * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 27*c62a0ac4Smatt * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 28*c62a0ac4Smatt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29*c62a0ac4Smatt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30*c62a0ac4Smatt * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 31*c62a0ac4Smatt * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 32*c62a0ac4Smatt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33*c62a0ac4Smatt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34*c62a0ac4Smatt * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35*c62a0ac4Smatt * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36*c62a0ac4Smatt * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37*c62a0ac4Smatt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 38*c62a0ac4Smatt * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39*c62a0ac4Smatt */ 40*c62a0ac4Smatt 41*c62a0ac4Smatt #ifndef _AT91SPIREG_H_ 42*c62a0ac4Smatt #define _AT91SPIREG_H_ 43*c62a0ac4Smatt 44*c62a0ac4Smatt #define SPI_CS_COUNT 4 45*c62a0ac4Smatt 46*c62a0ac4Smatt #define AT91_SPI_SIZE 0x4000U 47*c62a0ac4Smatt 48*c62a0ac4Smatt #define SPI_CR 0x00U /* 0x00: Control Register */ 49*c62a0ac4Smatt #define SPI_MR 0x04U /* 0x04: Mode Register */ 50*c62a0ac4Smatt #define SPI_RDR 0x08U /* 0x08: Receive Data Register */ 51*c62a0ac4Smatt #define SPI_TDR 0x0CU /* 0x0C: Transmit Data Register */ 52*c62a0ac4Smatt #define SPI_SR 0x10U /* 0x10: Status Register */ 53*c62a0ac4Smatt #define SPI_IER 0x14U /* 0x14: Interrupt Enable Reg */ 54*c62a0ac4Smatt #define SPI_IDR 0x18U /* 0x18: Interrupt Disable Reg */ 55*c62a0ac4Smatt #define SPI_IMR 0x1CU /* 0x1C: Interrupt Mask Reg */ 56*c62a0ac4Smatt #define SPI_CSR(slv) (0x30U + 4 * (slv)) /* 0x30: Chip Select Regs */ 57*c62a0ac4Smatt #define SPI_PDC_BASE 0x100U /* 0x100: PDC */ 58*c62a0ac4Smatt 59*c62a0ac4Smatt /* Control Register bits: */ 60*c62a0ac4Smatt #define SPI_CR_SWRST 0x80 /* 1 = Reset the SPI */ 61*c62a0ac4Smatt #define SPI_CR_SPIDIS 0x2 /* 1 = disables the SPI */ 62*c62a0ac4Smatt #define SPI_CR_SPIEN 0x1 /* 1 = enables the SPI */ 63*c62a0ac4Smatt 64*c62a0ac4Smatt /* Mode Register bits: */ 65*c62a0ac4Smatt #define SPI_MR_DLYBCS 0xFF000000 /* delay between chip selects */ 66*c62a0ac4Smatt #define SPI_MR_DLYBCS_SHIFT 24 67*c62a0ac4Smatt #define SPI_MR_PCS 0x000F0000 /* peripheral chip select */ 68*c62a0ac4Smatt #define SPI_MR_PCS_SHIFT 16 69*c62a0ac4Smatt #define SPI_MR_LLB 0x80 /* 1 = local loopback enabled */ 70*c62a0ac4Smatt #define SPI_MR_MODFDIS 0x10 /* 1 = mode fault detection dis */ 71*c62a0ac4Smatt #define SPI_MR_DIV32 0x08 /* 1 = SPI operates at MCK/32 */ 72*c62a0ac4Smatt #define SPI_MR_PCSDEC 0x04 /* 1 = use 4- to 16-bit decoder */ 73*c62a0ac4Smatt #define SPI_MR_PS 0x02 /* 1 = variable peripheral sel. */ 74*c62a0ac4Smatt #define SPI_MR_MSTR 0x01 /* 1 = SPI is in Master mode */ 75*c62a0ac4Smatt 76*c62a0ac4Smatt /* Status Register bits: */ 77*c62a0ac4Smatt #define SPI_SR_SPIENS 0x10000 /* 1 = SPI is enabled */ 78*c62a0ac4Smatt #define SPI_SR_TXBUFE 0x80 /* 1 = TX Buffer empty */ 79*c62a0ac4Smatt #define SPI_SR_RXBUFF 0x40 /* 1 = RX buffer full */ 80*c62a0ac4Smatt #define SPI_SR_ENDTX 0x20 /* 1 = End of TX buffer */ 81*c62a0ac4Smatt #define SPI_SR_ENDRX 0x10 /* 1 = End of RX buffer */ 82*c62a0ac4Smatt #define SPI_SR_OVRES 0x08 /* 1 = Overrun occurred */ 83*c62a0ac4Smatt #define SPI_SR_MODF 0x04 /* 1 = Mode fault occurred */ 84*c62a0ac4Smatt #define SPI_SR_TDRE 0x02 /* 1 = Transmit Data Reg empty */ 85*c62a0ac4Smatt #define SPI_SR_RDRF 0x01 /* 1 = Receive Data Reg full */ 86*c62a0ac4Smatt 87*c62a0ac4Smatt /* Chip Select Register: */ 88*c62a0ac4Smatt #define SPI_CSR_DLYBCT 0xFF000000 89*c62a0ac4Smatt #define SPI_CSR_DLYBCT_SHIFT 24 90*c62a0ac4Smatt #define SPI_CSR_DLYBS 0x00FF0000 91*c62a0ac4Smatt #define SPI_CSR_DLYBS_SHIFT 16 92*c62a0ac4Smatt #define SPI_CSR_SCBR 0x0000FF00 93*c62a0ac4Smatt #define SPI_CSR_SCBR_SHIFT 8 94*c62a0ac4Smatt #define SPI_CSR_BITS 0x000000F0 95*c62a0ac4Smatt #define SPI_CSR_BITS_8 (0U<<4) 96*c62a0ac4Smatt #define SPI_CSR_BITS_16 (8U<<4) 97*c62a0ac4Smatt #define SPI_CSR_BITS_SHIFT 4 98*c62a0ac4Smatt #define SPI_CSR_NCPHA 0x00000002 99*c62a0ac4Smatt #define SPI_CSR_CPOL 0x00000001 100*c62a0ac4Smatt #define SPI_CSR_RESERVED 0x0000000C 101*c62a0ac4Smatt 102*c62a0ac4Smatt #endif /* _AT91SPIREG_H_ */ 103