1*dbb1cf3fSaymeric /* $Id: at91pmcreg.h,v 1.3 2011/11/04 17:20:54 aymeric Exp $ */ 2c62a0ac4Smatt 3c62a0ac4Smatt #ifndef _AT91PMCREG_H_ 4c62a0ac4Smatt #define _AT91PMCREG_H_ 1 5c62a0ac4Smatt 6c62a0ac4Smatt /* Power Management Controller (PMC), at, 7c62a0ac4Smatt * at91rm9200.pdf, page 271 */ 8c62a0ac4Smatt 9c62a0ac4Smatt #define PMC_NUM_PCLOCKS 8 10c62a0ac4Smatt 11c62a0ac4Smatt #define PMC_SCER 0x00U /* 00: System Clock Enable Reg */ 12c62a0ac4Smatt #define PMC_SCDR 0x04U /* 04: System Clock Disable Reg */ 13c62a0ac4Smatt #define PMC_SCSR 0x08U /* 08: System Clock Status Reg */ 14c62a0ac4Smatt #define PMC_PCER 0x10U /* 10: Peripheral Clock Enable */ 15c62a0ac4Smatt #define PMC_PCDR 0x14U /* 14: Peripheral Clock Disable */ 16c62a0ac4Smatt #define PMC_PCSR 0x18U /* 18: Peripheral Clock Status */ 17c62a0ac4Smatt #define PMC_MOR 0x20U /* 20: Main Oscillator Reg */ 18c62a0ac4Smatt #define PMC_MCFR 0x24U /* 24: Main Clock Freq Reg */ 19c62a0ac4Smatt #define PMC_PLLAR 0x28U /* 28: PLL A Register#define PMC_*/ 20c62a0ac4Smatt #define PMC_PLLBR 0x2CU /* 2C: PLL B Register */ 21c62a0ac4Smatt #define PMC_MCKR 0x30U /* 30: Master Clock Register */ 22c62a0ac4Smatt #define PMC_PCK(num) (0x40U + (num) * 4U) /* 40: Programmable Clocks */ 23c62a0ac4Smatt #define PMC_IER 0x60U /* 60: Interrupt Enable Reg */ 24c62a0ac4Smatt #define PMC_IDR 0x64U /* 64: Interrupt Disable Reg */ 25c62a0ac4Smatt #define PMC_SR 0x68U /* 68: Status Register */ 26c62a0ac4Smatt #define PMC_IMR 0x6CU /* 6C: Interrupt Mask Reg */ 27*dbb1cf3fSaymeric #define PMC_PLLICPR 0x80U /* 80: PLL Charge Pump Current Reg */ 28c62a0ac4Smatt 29c62a0ac4Smatt /* System Clock Enable Register bits: */ 30c62a0ac4Smatt #define PMC_SCSR_PCK3 0x0800U 31c62a0ac4Smatt #define PMC_SCSR_PCK2 0x0400U 32c62a0ac4Smatt #define PMC_SCSR_PCK1 0x0200U 33c62a0ac4Smatt #define PMC_SCSR_PCK0 0x0100U 34*dbb1cf3fSaymeric #define PMC_SCSR_SAM_UDP 0x0080U 35*dbb1cf3fSaymeric #define PMC_SCSR_SAM_UHP 0x0040U 36c62a0ac4Smatt #define PMC_SCSR_UHP 0x0010U /* 1 = Enable USB Host Port clks */ 37c62a0ac4Smatt #define PMC_SCSR_MCKUDP 0x0004U /* 1 = enable Master Clock dis */ 38c62a0ac4Smatt #define PMC_SCSR_UDP 0x0002U /* 1 = enable USB Device Port clk */ 39c62a0ac4Smatt #define PMC_SCSR_PCK 0x0001U /* 1 = enable the processor clk */ 40c62a0ac4Smatt 41c62a0ac4Smatt /* Main Oscillator Register bits: */ 42c62a0ac4Smatt #define PMC_MOR_OSCOUNT 0xFF00U /* start-up-time / 8 */ 43c62a0ac4Smatt #define PMC_MOR_OSCOUNT_SHIFT 8U 44c62a0ac4Smatt #define PMC_MOR_MOSCEN 0x1U /* 1 = main oscillator enabled */ 45c62a0ac4Smatt 46c62a0ac4Smatt /* Main Clock Frequency Register bits: */ 47c62a0ac4Smatt #define PMC_MCFR_MAINRDY 0x10000U /* 1= main clock ready */ 48c62a0ac4Smatt #define PMC_MCFR_MAINF 0x0FFFFU 49c62a0ac4Smatt 50c62a0ac4Smatt /* PLL Register bits: */ 51c62a0ac4Smatt #define PMC_PLL_MUL 0x07FF0000U 52c62a0ac4Smatt #define PMC_PLL_MUL_SHIFT 16U 53c62a0ac4Smatt #define PMC_PLL_OUT 0x0000C000U 54c62a0ac4Smatt #define PMC_PLL_OUT_80_TO_160 0x00000000U 55c62a0ac4Smatt #define PMC_PLL_OUT_150_TO_240 0x00008000U 56c62a0ac4Smatt #define PMC_PLL_PLLCOUNT 0x00003F00U 57c62a0ac4Smatt #define PMC_PLL_DIV 0x000000FFU 58c62a0ac4Smatt #define PMC_PLL_DIV_SHIFT 0U 59c62a0ac4Smatt 60c62a0ac4Smatt /* PLL B Register bits: */ 61c62a0ac4Smatt #define PMC_PLLBR_USB_96M 0x10000000U /* 1 = USB clks = PLL B output / 2 */ 62c62a0ac4Smatt 63c62a0ac4Smatt /* Master Clock Register bits: */ 64c62a0ac4Smatt #define PMC_MCKR_MDIV 0x300U 65c62a0ac4Smatt #define PMC_MCKR_MDIV_1 0x000U 66c62a0ac4Smatt #define PMC_MCKR_MDIV_2 0x100U 67c62a0ac4Smatt #define PMC_MCKR_MDIV_3 0x200U 68c62a0ac4Smatt #define PMC_MCKR_MDIV_4 0x300U 69c62a0ac4Smatt #define PMC_MCKR_MDIV_SHIFT 8U 70c62a0ac4Smatt 71c62a0ac4Smatt #define PMC_MCKR_PRES 0x01CU 72c62a0ac4Smatt #define PMC_MCKR_PRES_SHIFT 2U 73c62a0ac4Smatt #define PMC_MCKR_PRES_1 (0U<<PMC_MCKR_PRES_SHIFT) 74c62a0ac4Smatt #define PMC_MCKR_PRES_2 (1U<<PMC_MCKR_PRES_SHIFT) 75c62a0ac4Smatt #define PMC_MCKR_PRES_4 (2U<<PMC_MCKR_PRES_SHIFT) 76c62a0ac4Smatt #define PMC_MCKR_PRES_8 (3U<<PMC_MCKR_PRES_SHIFT) 77c62a0ac4Smatt #define PMC_MCKR_PRES_16 (4U<<PMC_MCKR_PRES_SHIFT) 78c62a0ac4Smatt #define PMC_MCKR_PRES_32 (5U<<PMC_MCKR_PRES_SHIFT) 79c62a0ac4Smatt #define PMC_MCKR_PRES_64 (6U<<PMC_MCKR_PRES_SHIFT) 80c62a0ac4Smatt 81c62a0ac4Smatt #define PMC_MCKR_CSS 0x003U 82c62a0ac4Smatt #define PMC_MCKR_CSS_SLOW_CLK 0x000U 83c62a0ac4Smatt #define PMC_MCKR_CSS_MAIN_CLK 0x001U 84c62a0ac4Smatt #define PMC_MCKR_CSS_PLLA 0x002U 85c62a0ac4Smatt #define PMC_MCKR_CSS_PLLB 0x003U 86c62a0ac4Smatt 87c62a0ac4Smatt /* Programmable Clock Register bits: */ 88c62a0ac4Smatt #define PMC_PCK_PRES PMC_MCKR_PRES 89c62a0ac4Smatt #define PMC_PCK_PRES_SHIFT PMC_MCKR_PRES_SHIFT 90c62a0ac4Smatt #define PMC_PCK_PRES_1 PMC_MCKR_PRES_1 91c62a0ac4Smatt #define PMC_PCK_PRES_2 PMC_MCKR_PRES_2 92c62a0ac4Smatt #define PMC_PCK_PRES_4 PMC_MCKR_PRES_4 93c62a0ac4Smatt #define PMC_PCK_PRES_8 PMC_MCKR_PRES_8 94c62a0ac4Smatt #define PMC_PCK_PRES_16 PMC_MCKR_PRES_16 95c62a0ac4Smatt #define PMC_PCK_PRES_32 PMC_MCKR_PRES_32 96c62a0ac4Smatt #define PMC_PCK_PRES_64 PMC_MCKR_PRES_64 97c62a0ac4Smatt 98c62a0ac4Smatt #define PMC_PCK_CSS PMC_MCKR_CSS 99c62a0ac4Smatt #define PMC_PCK_CSS_SLOW_CLK PMC_MCKR_CSS_SLOW_CLK 100c62a0ac4Smatt #define PMC_PCK_CSS_CLKC PMC_MCKR_CSS_CLKC 101c62a0ac4Smatt #define PMC_PCK_CSS_CLKA PMC_MCKR_CSS_CLKA 102c62a0ac4Smatt #define PMC_PCK_CSS_CLKB PMC_MCKR_CSS_CLKB 103c62a0ac4Smatt 104c62a0ac4Smatt 105c62a0ac4Smatt /* Interrupt Enable Register bits: */ 106c62a0ac4Smatt #define PMC_SR_PCK7RDY 0x8000U 107c62a0ac4Smatt #define PMC_SR_PCK6RDY 0x4000U 108c62a0ac4Smatt #define PMC_SR_PCK5RDY 0x2000U 109c62a0ac4Smatt #define PMC_SR_PCK4RDY 0x1000U 110c62a0ac4Smatt #define PMC_SR_PCK3RDY 0x0800U 111c62a0ac4Smatt #define PMC_SR_PCK2RDY 0x0400U 112c62a0ac4Smatt #define PMC_SR_PCK1RDY 0x0200U 113c62a0ac4Smatt #define PMC_SR_PCK0RDY 0x0100U 114c62a0ac4Smatt #define PMC_SR_MCKRDY 0x0008U 115c62a0ac4Smatt #define PMC_SR_LOCKB 0x0004U 116c62a0ac4Smatt #define PMC_SR_LOCKA 0x0002U 117c62a0ac4Smatt #define PMC_SR_MOSCS 0x0001U 118c62a0ac4Smatt 119*dbb1cf3fSaymeric /* PLL Charge Pump Current Reg bits: */ 120*dbb1cf3fSaymeric #define PMC_PLLICPR_ICPPLLA 0x00000001U 121*dbb1cf3fSaymeric #define PMC_PLLICPR_ICPPLLB 0x00010000U 122*dbb1cf3fSaymeric 123c62a0ac4Smatt #define PMCREG(offset) *((volatile uint32_t*)(0xfffffc00UL + (offset))) 124c62a0ac4Smatt 125c62a0ac4Smatt #endif /* !_AT91PMCREG_H_ */ 126