xref: /netbsd-src/sys/arch/arm/at91/at91pmc.c (revision 4c1762c6a4e5d067a7ed20b55f6cc4f4a4eb5a4a)
1*4c1762c6Srin /*	$Id: at91pmc.c,v 1.8 2020/02/24 12:38:57 rin Exp $	*/
2*4c1762c6Srin /*	$NetBSD: at91pmc.c,v 1.8 2020/02/24 12:38:57 rin Exp $	*/
3c62a0ac4Smatt 
4c62a0ac4Smatt /*
5c62a0ac4Smatt  * Copyright (c) 2007 Embedtronics Oy
6c62a0ac4Smatt  * All rights reserved.
7c62a0ac4Smatt  *
8c62a0ac4Smatt  * Redistribution and use in source and binary forms, with or without
9c62a0ac4Smatt  * modification, are permitted provided that the following conditions
10c62a0ac4Smatt  * are met:
11c62a0ac4Smatt  * 1. Redistributions of source code must retain the above copyright
12c62a0ac4Smatt  *    notice, this list of conditions and the following disclaimer.
13c62a0ac4Smatt  * 2. Redistributions in binary form must reproduce the above copyright
14c62a0ac4Smatt  *    notice, this list of conditions and the following disclaimer in the
15c62a0ac4Smatt  *    documentation and/or other materials provided with the distribution.
16c62a0ac4Smatt  *
17c62a0ac4Smatt  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18c62a0ac4Smatt  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19c62a0ac4Smatt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20c62a0ac4Smatt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21c62a0ac4Smatt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22c62a0ac4Smatt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23c62a0ac4Smatt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24c62a0ac4Smatt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25c62a0ac4Smatt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26c62a0ac4Smatt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27c62a0ac4Smatt  * POSSIBILITY OF SUCH DAMAGE.
28c62a0ac4Smatt  */
29c62a0ac4Smatt 
30c62a0ac4Smatt #include <sys/cdefs.h>
31*4c1762c6Srin __KERNEL_RCSID(0, "$NetBSD: at91pmc.c,v 1.8 2020/02/24 12:38:57 rin Exp $");
32c62a0ac4Smatt 
33c62a0ac4Smatt #include <sys/types.h>
34c62a0ac4Smatt #include <sys/param.h>
35c62a0ac4Smatt #include <sys/systm.h>
36c62a0ac4Smatt #include <sys/kernel.h>
37c62a0ac4Smatt #include <sys/time.h>
38c62a0ac4Smatt #include <sys/device.h>
39c62a0ac4Smatt 
40cf10107dSdyoung #include <sys/bus.h>
41c62a0ac4Smatt #include <machine/intr.h>
42c62a0ac4Smatt 
43c62a0ac4Smatt #include <arm/cpufunc.h>
44c62a0ac4Smatt 
45c62a0ac4Smatt #include <arm/at91/at91reg.h>
46c62a0ac4Smatt #include <arm/at91/at91var.h>
47c62a0ac4Smatt #include <arm/at91/at91pmcreg.h>
48c62a0ac4Smatt #include <arm/at91/at91pmcvar.h>
49c62a0ac4Smatt 
50c62a0ac4Smatt #define	SLOW_CLOCK	32768LU
51c62a0ac4Smatt 
52c62a0ac4Smatt void
at91pmc_get_clocks(struct at91bus_clocks * clocks)53c62a0ac4Smatt at91pmc_get_clocks(struct at91bus_clocks *clocks)
54c62a0ac4Smatt {
5508a4aba7Sskrll 	uint64_t		mclk, pllaclk, pllbclk, pclk, mstclk;
5608a4aba7Sskrll 	uint32_t		reg;
57c62a0ac4Smatt 
58c62a0ac4Smatt 	if (!((reg = PMCREG(PMC_MOR)) & PMC_MOR_MOSCEN))
59*4c1762c6Srin 		panic("%s: main oscillator not enabled (MOR=%#X)", __FUNCTION__, reg);
60c62a0ac4Smatt 
61c62a0ac4Smatt 	if (!((reg = PMCREG(PMC_MCFR)) & PMC_MCFR_MAINRDY))
62*4c1762c6Srin 		panic("%s: main oscillator not ready (MCFR=%#X)", __FUNCTION__, reg);
63c62a0ac4Smatt 
64c62a0ac4Smatt 	mclk  = ((reg & PMC_MCFR_MAINF) * SLOW_CLOCK) / 16U;
65c62a0ac4Smatt 
66c62a0ac4Smatt 	// try to guess some nice MHz value
67c62a0ac4Smatt 	if (((mclk / 1000) % 1000) >= 990) {
68c62a0ac4Smatt 	  mclk += 1000000U - (mclk % 1000000U);
69c62a0ac4Smatt 	} else if (((mclk / 1000) % 1000) <= 10) {
70c62a0ac4Smatt 	  mclk -= (mclk % 1000000U);
71c62a0ac4Smatt 	}
72c62a0ac4Smatt 
73acbbb2d9Saymeric 	PMCREG(PMC_PLLICPR) = PMC_PLLICPR_ICPPLLA | PMC_PLLICPR_ICPPLLB;
74acbbb2d9Saymeric 
75c62a0ac4Smatt 	reg = PMCREG(PMC_PLLAR); pllaclk = 0;
76c62a0ac4Smatt 	if (reg & PMC_PLL_DIV) {
77c62a0ac4Smatt 		pllaclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);
78c62a0ac4Smatt 		pllaclk /= (reg & PMC_PLL_DIV) >> PMC_PLL_DIV_SHIFT;
79c62a0ac4Smatt 	}
80c62a0ac4Smatt 
81c62a0ac4Smatt 	reg = PMCREG(PMC_PLLBR); pllbclk = 0;
82c62a0ac4Smatt 	if (reg & PMC_PLL_DIV) {
83c62a0ac4Smatt 		pllbclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);
84c62a0ac4Smatt 		pllbclk /= (reg & PMC_PLL_DIV) >> PMC_PLL_DIV_SHIFT;
85c62a0ac4Smatt 		if (reg & PMC_PLLBR_USB_96M) {
86c62a0ac4Smatt 			pllbclk /= 2;
87c62a0ac4Smatt 		}
88c62a0ac4Smatt 	}
89c62a0ac4Smatt 
90c62a0ac4Smatt 	reg = PMCREG(PMC_MCKR);
91c62a0ac4Smatt 	switch ((reg & PMC_MCKR_CSS)) {
92c62a0ac4Smatt 	case PMC_MCKR_CSS_SLOW_CLK:
93c62a0ac4Smatt 	  pclk = SLOW_CLOCK;
94c62a0ac4Smatt 	  break;
95c62a0ac4Smatt 	default:
96c62a0ac4Smatt 	case PMC_MCKR_CSS_MAIN_CLK:
97c62a0ac4Smatt 	  pclk = mclk;
98c62a0ac4Smatt 	  break;
99c62a0ac4Smatt 	case PMC_MCKR_CSS_PLLA:
100c62a0ac4Smatt 	  pclk = pllaclk;
101c62a0ac4Smatt 	  break;
102c62a0ac4Smatt 	case PMC_MCKR_CSS_PLLB:
103c62a0ac4Smatt 	  pclk = pllbclk;
104c62a0ac4Smatt 	  break;
105c62a0ac4Smatt 	}
106c62a0ac4Smatt 	pclk >>= (reg & PMC_MCKR_PRES) >> PMC_MCKR_PRES_SHIFT;
107c62a0ac4Smatt 	mstclk = pclk / (((reg & PMC_MCKR_MDIV) >> PMC_MCKR_MDIV_SHIFT) + 1);
108c62a0ac4Smatt 
109c62a0ac4Smatt 	clocks->slow = SLOW_CLOCK;
110c62a0ac4Smatt 	clocks->main = mclk;
111c62a0ac4Smatt 	clocks->cpu = pclk;
112c62a0ac4Smatt 	clocks->master = mstclk;
113c62a0ac4Smatt 	clocks->plla = pllaclk;
114c62a0ac4Smatt 	clocks->pllb = pllbclk;
115c62a0ac4Smatt }
116c62a0ac4Smatt 
117c62a0ac4Smatt 
118c62a0ac4Smatt #define	PID_COUNT	32
119c62a0ac4Smatt static int pid_enable_count[PID_COUNT] = {0};
120c62a0ac4Smatt 
121c62a0ac4Smatt void
at91pmc_peripheral_clock(int pid,int enable)122c62a0ac4Smatt at91pmc_peripheral_clock(int pid, int enable)
123c62a0ac4Smatt {
124c62a0ac4Smatt 	int s;
125c62a0ac4Smatt 
126c62a0ac4Smatt 	if (pid < 0 || pid >= PID_COUNT)
127c62a0ac4Smatt 		panic("%s: pid %d out of range", __FUNCTION__, pid);
128c62a0ac4Smatt 
129c62a0ac4Smatt 	s = splhigh();
130c62a0ac4Smatt 
131c62a0ac4Smatt 	if (enable) {
132c62a0ac4Smatt 		pid_enable_count[pid]++;
133c62a0ac4Smatt 		PMCREG(PMC_PCER) = (1U << pid);
134c62a0ac4Smatt 	} else {
135c62a0ac4Smatt 		if (--pid_enable_count[pid] < 0)
136c62a0ac4Smatt 			panic("%s: pid %d enable count got negative (%d)",
137c62a0ac4Smatt 			      __FUNCTION__, pid, pid_enable_count[pid]);
138c62a0ac4Smatt 		if (pid_enable_count[pid] == 0)
139c62a0ac4Smatt 			PMCREG(PMC_PCDR) = (1U << pid);
140c62a0ac4Smatt 	}
141c62a0ac4Smatt 
142c62a0ac4Smatt 	splx(s);
143c62a0ac4Smatt 
144c62a0ac4Smatt 	if (enable) {
145c62a0ac4Smatt 		int c;
146c62a0ac4Smatt 		for (c = 0; c < 10000; c++) {
147c62a0ac4Smatt 		  __insn_barrier();
148c62a0ac4Smatt 		}
149c62a0ac4Smatt 	}
150c62a0ac4Smatt }
151