1*cff5caddSsnj /* $NetBSD: at91pdcreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 2c62a0ac4Smatt 3c62a0ac4Smatt /* 4c62a0ac4Smatt * Copyright (c) 2007 Embedtronics Oy. 5c62a0ac4Smatt * All rights reserved. 6c62a0ac4Smatt * 7c62a0ac4Smatt * Redistribution and use in source and binary forms, with or without 8c62a0ac4Smatt * modification, are permitted provided that the following conditions 9c62a0ac4Smatt * are met: 10c62a0ac4Smatt * 1. Redistributions of source code must retain the above copyright 11c62a0ac4Smatt * notice, this list of conditions and the following disclaimer. 12c62a0ac4Smatt * 2. Redistributions in binary form must reproduce the above copyright 13c62a0ac4Smatt * notice, this list of conditions and the following disclaimer in the 14c62a0ac4Smatt * documentation and/or other materials provided with the distribution. 15c62a0ac4Smatt * 16c62a0ac4Smatt * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 17c62a0ac4Smatt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18c62a0ac4Smatt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19c62a0ac4Smatt * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 20c62a0ac4Smatt * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21c62a0ac4Smatt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22c62a0ac4Smatt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23c62a0ac4Smatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24c62a0ac4Smatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25c62a0ac4Smatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26c62a0ac4Smatt * SUCH DAMAGE. 27c62a0ac4Smatt */ 28c62a0ac4Smatt 29c62a0ac4Smatt #ifndef _AT91PDCREG_H_ 30c62a0ac4Smatt #define _AT91PDCREG_H_ 31c62a0ac4Smatt 32c62a0ac4Smatt #define PDC_RPR 0x00UL /* Receive Pointer Register */ 33c62a0ac4Smatt #define PDC_RCR 0x04UL /* Receive Counter Register */ 34c62a0ac4Smatt #define PDC_TPR 0x08UL /* Transmit Pointer Register */ 35c62a0ac4Smatt #define PDC_TCR 0x0CUL /* Transmit Counter Register */ 36c62a0ac4Smatt #define PDC_RNPR 0x10UL /* Receive Next Pointer Reg */ 37c62a0ac4Smatt #define PDC_RNCR 0x14UL /* Receive Next Counter Reg */ 38c62a0ac4Smatt #define PDC_TNPR 0x18UL /* Transmit Next Ptt Register */ 39c62a0ac4Smatt #define PDC_TNCR 0x1CUL /* Transmit Next Counter Reg */ 40c62a0ac4Smatt #define PDC_PTCR 0x20UL /* PDC Transfer Ctl Reg PDC_ */ 41c62a0ac4Smatt #define PDC_PTSR 0x24UL /* PDC Transfer Status Reg */ 42c62a0ac4Smatt 43c62a0ac4Smatt /* Transfer Control Register bits: */ 44c62a0ac4Smatt #define PDC_PTCR_TXTDIS 0x200 /* disable transmitter */ 45c62a0ac4Smatt #define PDC_PTCR_TXTEN 0x100 /* enable transmitter */ 46c62a0ac4Smatt #define PDC_PTCR_RXTDIS 0x002 /* disable receiver */ 47c62a0ac4Smatt #define PDC_PTCR_RXTEN 0x001 /* enable receiver */ 48c62a0ac4Smatt 49c62a0ac4Smatt /* Transfer Status Register bits: */ 50c62a0ac4Smatt #define PDC_PTSR_TXTEN PDC_PTCR_TXTEN 51c62a0ac4Smatt #define PDC_PTSR_RXTEN PDC_PTCR_RXTEN 52c62a0ac4Smatt 53c62a0ac4Smatt #endif // _AT91PDCREG_H_ 54c62a0ac4Smatt 55