1*496e2b65Sskrll /* $NetBSD: ast.c,v 1.32 2021/02/01 19:31:34 skrll Exp $ */
200bd2cbdSbjh21
300bd2cbdSbjh21 /*
400bd2cbdSbjh21 * Copyright (c) 1994,1995 Mark Brinicombe
500bd2cbdSbjh21 * All rights reserved.
600bd2cbdSbjh21 *
700bd2cbdSbjh21 * Redistribution and use in source and binary forms, with or without
800bd2cbdSbjh21 * modification, are permitted provided that the following conditions
900bd2cbdSbjh21 * are met:
1000bd2cbdSbjh21 * 1. Redistributions of source code must retain the above copyright
1100bd2cbdSbjh21 * notice, this list of conditions and the following disclaimer.
1200bd2cbdSbjh21 * 2. Redistributions in binary form must reproduce the above copyright
1300bd2cbdSbjh21 * notice, this list of conditions and the following disclaimer in the
1400bd2cbdSbjh21 * documentation and/or other materials provided with the distribution.
1500bd2cbdSbjh21 * 3. All advertising materials mentioning features or use of this software
1600bd2cbdSbjh21 * must display the following acknowledgement:
1700bd2cbdSbjh21 * This product includes software developed by the RiscBSD team.
1800bd2cbdSbjh21 * 4. The name of the company nor the name of the author may be used to
1900bd2cbdSbjh21 * endorse or promote products derived from this software without specific
2000bd2cbdSbjh21 * prior written permission.
2100bd2cbdSbjh21 *
2200bd2cbdSbjh21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
2300bd2cbdSbjh21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2400bd2cbdSbjh21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
2500bd2cbdSbjh21 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
2600bd2cbdSbjh21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2700bd2cbdSbjh21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
2800bd2cbdSbjh21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2900bd2cbdSbjh21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
3000bd2cbdSbjh21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
3100bd2cbdSbjh21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
3200bd2cbdSbjh21 * SUCH DAMAGE.
3300bd2cbdSbjh21 *
3400bd2cbdSbjh21 * RiscBSD kernel project
3500bd2cbdSbjh21 *
3600bd2cbdSbjh21 * ast.c
3700bd2cbdSbjh21 *
3800bd2cbdSbjh21 * Code to handle ast's and returns to user mode
3900bd2cbdSbjh21 *
4000bd2cbdSbjh21 * Created : 11/10/94
4100bd2cbdSbjh21 */
4200bd2cbdSbjh21
4308716eaeSlukem #include <sys/cdefs.h>
44*496e2b65Sskrll __KERNEL_RCSID(0, "$NetBSD: ast.c,v 1.32 2021/02/01 19:31:34 skrll Exp $");
4508716eaeSlukem
4600bd2cbdSbjh21 #include "opt_ddb.h"
4700bd2cbdSbjh21
4800bd2cbdSbjh21 #include <sys/param.h>
49ab152917Smatt #include <sys/cpu.h>
5000bd2cbdSbjh21 #include <sys/proc.h>
5100bd2cbdSbjh21 #include <sys/acct.h>
5200bd2cbdSbjh21 #include <sys/systm.h>
534a6cf9c0Smatt #include <sys/atomic.h>
5400bd2cbdSbjh21 #include <sys/kernel.h>
5500bd2cbdSbjh21 #include <sys/signal.h>
56ef56cc40Scl #include <sys/userret.h>
574a6cf9c0Smatt #include <sys/vmmeter.h>
58ef56cc40Scl
59ab152917Smatt #include <arm/locore.h>
6000bd2cbdSbjh21
6100bd2cbdSbjh21 #include <uvm/uvm_extern.h>
6200bd2cbdSbjh21
63e3a3a9f5Schris /*
64e3a3a9f5Schris * Prototypes
65e3a3a9f5Schris */
66825088edSmatt void ast(struct trapframe *);
6700bd2cbdSbjh21
6800bd2cbdSbjh21 void
userret(struct lwp * l)6923bc2503Sthorpej userret(struct lwp *l)
7000bd2cbdSbjh21 {
71ac344355Sskrll #if defined(ARM_MMU_EXTENDED)
72ac5d706aSmatt /*
73ac5d706aSmatt * If our ASID got released, access via TTBR0 will have been disabled.
74ac5d706aSmatt * So if it is disabled, activate the lwp again to get a new ASID.
75ac5d706aSmatt */
764a6cf9c0Smatt #ifdef __HAVE_PREEMPTION
774a6cf9c0Smatt kpreempt_disable();
784a6cf9c0Smatt #endif
791ab746dbSskrll KASSERTMSG(curcpu()->ci_pmap_cur == l->l_proc->p_vmspace->vm_map.pmap,
801ab746dbSskrll "%p vs %p", curcpu()->ci_pmap_cur,
811ab746dbSskrll l->l_proc->p_vmspace->vm_map.pmap);
824a6cf9c0Smatt if (__predict_false(armreg_ttbcr_read() & TTBCR_S_PD0)) {
83ac5d706aSmatt pmap_activate(l);
84ac5d706aSmatt }
85cf508629Sskrll KASSERT(!(armreg_ttbcr_read() & TTBCR_S_PD0));
864a6cf9c0Smatt #ifdef __HAVE_PREEMPTION
874a6cf9c0Smatt kpreempt_enable();
884a6cf9c0Smatt #endif
89ac5d706aSmatt #endif
90ac5d706aSmatt
91cf508629Sskrll /* Invoke MI userret code */
92cf508629Sskrll mi_userret(l);
93cf508629Sskrll
94*496e2b65Sskrll KASSERT(VALID_PSR(lwp_trapframe(l)->tf_spsr));
9500bd2cbdSbjh21 }
9600bd2cbdSbjh21
9700bd2cbdSbjh21
9800bd2cbdSbjh21 /*
9900bd2cbdSbjh21 * Handle asynchronous system traps.
10000bd2cbdSbjh21 * This is called from the irq handler to deliver signals
10100bd2cbdSbjh21 * and switch processes if required.
10200bd2cbdSbjh21 */
10300bd2cbdSbjh21
10400bd2cbdSbjh21 void
ast(struct trapframe * tf)10500bd2cbdSbjh21 ast(struct trapframe *tf)
10600bd2cbdSbjh21 {
107445ebaadSmatt struct lwp * const l = curlwp;
10800bd2cbdSbjh21
10900bd2cbdSbjh21 /* Interrupts were restored by exception_exit. */
11000bd2cbdSbjh21
111*496e2b65Sskrll KASSERT(VALID_PSR(tf->tf_spsr));
112c3660f1dSmatt
1136c004530Sjmcneill #ifdef __HAVE_PREEMPTION
1144a6cf9c0Smatt kpreempt_disable();
1154a6cf9c0Smatt #endif
1164a6cf9c0Smatt struct cpu_info * const ci = curcpu();
11700bd2cbdSbjh21
1184a6cf9c0Smatt ci->ci_data.cpu_ntrap++;
1194a6cf9c0Smatt
1204a6cf9c0Smatt KDASSERT(ci->ci_cpl == IPL_NONE);
1216c004530Sjmcneill #ifdef __HAVE_PREEMPTION
1224a6cf9c0Smatt kpreempt_enable();
12300bd2cbdSbjh21 #endif
12400bd2cbdSbjh21
125c51fe070Smatt if (l->l_pflag & LP_OWEUPC) {
126c51fe070Smatt l->l_pflag &= ~LP_OWEUPC;
127992269c5Snjoly ADDUPROF(l);
12800bd2cbdSbjh21 }
12900bd2cbdSbjh21
13023bc2503Sthorpej userret(l);
13100bd2cbdSbjh21 }
132