xref: /netbsd-src/sys/arch/arm/acpi/acpi_pci_n1sdp.c (revision 5158b98c3ad5629f6fdc5db5d57b396373690489)
1*5158b98cSjmcneill /* $NetBSD: acpi_pci_n1sdp.c,v 1.7 2022/10/15 11:07:38 jmcneill Exp $ */
26f25f864Sjmcneill 
36f25f864Sjmcneill /*-
46f25f864Sjmcneill  * Copyright (c) 2020 The NetBSD Foundation, Inc.
56f25f864Sjmcneill  * All rights reserved.
66f25f864Sjmcneill  *
76f25f864Sjmcneill  * This code is derived from software contributed to The NetBSD Foundation
86f25f864Sjmcneill  * by Jared McNeill <jmcneill@invisible.ca>.
96f25f864Sjmcneill  *
106f25f864Sjmcneill  * Redistribution and use in source and binary forms, with or without
116f25f864Sjmcneill  * modification, are permitted provided that the following conditions
126f25f864Sjmcneill  * are met:
136f25f864Sjmcneill  * 1. Redistributions of source code must retain the above copyright
146f25f864Sjmcneill  *    notice, this list of conditions and the following disclaimer.
156f25f864Sjmcneill  * 2. Redistributions in binary form must reproduce the above copyright
166f25f864Sjmcneill  *    notice, this list of conditions and the following disclaimer in the
176f25f864Sjmcneill  *    documentation and/or other materials provided with the distribution.
186f25f864Sjmcneill  *
196f25f864Sjmcneill  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
206f25f864Sjmcneill  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
216f25f864Sjmcneill  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
226f25f864Sjmcneill  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
236f25f864Sjmcneill  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
246f25f864Sjmcneill  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
256f25f864Sjmcneill  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
266f25f864Sjmcneill  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
276f25f864Sjmcneill  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
286f25f864Sjmcneill  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
296f25f864Sjmcneill  * POSSIBILITY OF SUCH DAMAGE.
306f25f864Sjmcneill  */
316f25f864Sjmcneill 
326f25f864Sjmcneill #include <sys/cdefs.h>
33*5158b98cSjmcneill __KERNEL_RCSID(0, "$NetBSD: acpi_pci_n1sdp.c,v 1.7 2022/10/15 11:07:38 jmcneill Exp $");
346f25f864Sjmcneill 
356f25f864Sjmcneill #include <sys/param.h>
366f25f864Sjmcneill #include <sys/bus.h>
376f25f864Sjmcneill #include <sys/device.h>
386f25f864Sjmcneill #include <sys/intr.h>
396f25f864Sjmcneill #include <sys/systm.h>
406f25f864Sjmcneill #include <sys/kernel.h>
416f25f864Sjmcneill #include <sys/kmem.h>
42cf660908Sad #include <sys/cpu.h>
436f25f864Sjmcneill 
446f25f864Sjmcneill #include <dev/pci/pcireg.h>
456f25f864Sjmcneill #include <dev/pci/pcivar.h>
466f25f864Sjmcneill #include <dev/pci/pciconf.h>
476f25f864Sjmcneill 
486f25f864Sjmcneill #include <dev/acpi/acpivar.h>
496f25f864Sjmcneill #include <dev/acpi/acpi_pci.h>
506f25f864Sjmcneill #include <dev/acpi/acpi_mcfg.h>
516f25f864Sjmcneill 
526f25f864Sjmcneill #include <arm/acpi/acpi_pci_machdep.h>
536f25f864Sjmcneill 
546f25f864Sjmcneill extern struct bus_space arm_generic_bs_tag;
556f25f864Sjmcneill 
566f25f864Sjmcneill /* Shared memory location written by the SCP at boot */
576f25f864Sjmcneill #define	N1SDP_SHARED_MEM_BASE	0x06000000
586f25f864Sjmcneill 
596f25f864Sjmcneill #define	N1SDP_NSEGS		2
606f25f864Sjmcneill #define	N1SDP_TABLE_SIZE	0x4000
616f25f864Sjmcneill 
626f25f864Sjmcneill #define	N1SDP_BUS_SHIFT		20
636f25f864Sjmcneill #define	N1SDP_DEV_SHIFT		15
646f25f864Sjmcneill #define	N1SDP_FUNC_SHIFT	12
656f25f864Sjmcneill 
666f25f864Sjmcneill struct n1sdp_pcie_discovery_data {
676f25f864Sjmcneill 	uint32_t	rc_base_addr;
686f25f864Sjmcneill 	uint32_t	nr_bdfs;
696f25f864Sjmcneill 	uint32_t	valid_bdfs[0];
706f25f864Sjmcneill };
716f25f864Sjmcneill 
726f25f864Sjmcneill static struct n1sdp_pcie_discovery_data *n1sdp_data[N1SDP_NSEGS];
736f25f864Sjmcneill 
746f25f864Sjmcneill static bool
acpi_pci_n1sdp_valid(pci_chipset_tag_t pc,pcitag_t tag)756f25f864Sjmcneill acpi_pci_n1sdp_valid(pci_chipset_tag_t pc, pcitag_t tag)
766f25f864Sjmcneill {
776f25f864Sjmcneill 	struct acpi_pci_context *ap = pc->pc_conf_v;
786f25f864Sjmcneill 	u_int n, bdfaddr;
796f25f864Sjmcneill 	int b, d, f;
806f25f864Sjmcneill 
816f25f864Sjmcneill 	if (ap->ap_seg >= N1SDP_NSEGS || n1sdp_data[ap->ap_seg] == NULL)
826f25f864Sjmcneill 		return false;
836f25f864Sjmcneill 
846f25f864Sjmcneill 	pci_decompose_tag(pc, tag, &b, &d, &f);
856f25f864Sjmcneill 
866f25f864Sjmcneill 	bdfaddr = (b << N1SDP_BUS_SHIFT) +
876f25f864Sjmcneill 		  (d << N1SDP_DEV_SHIFT) +
886f25f864Sjmcneill 		  (f << N1SDP_FUNC_SHIFT);
896f25f864Sjmcneill 
906f25f864Sjmcneill 	for (n = 0; n < n1sdp_data[ap->ap_seg]->nr_bdfs; n++) {
916f25f864Sjmcneill 		if (n1sdp_data[ap->ap_seg]->valid_bdfs[n] == bdfaddr)
926f25f864Sjmcneill 			return true;
936f25f864Sjmcneill 	}
946f25f864Sjmcneill 
956f25f864Sjmcneill 	return false;
966f25f864Sjmcneill }
976f25f864Sjmcneill 
986f25f864Sjmcneill static int
acpi_pci_n1sdp_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t * data)996f25f864Sjmcneill acpi_pci_n1sdp_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)
1006f25f864Sjmcneill {
1016f25f864Sjmcneill 	struct acpi_pci_context *ap = pc->pc_conf_v;
1026f25f864Sjmcneill 	int b, d, f;
1036f25f864Sjmcneill 
1046f25f864Sjmcneill 	pci_decompose_tag(pc, tag, &b, &d, &f);
1056f25f864Sjmcneill 
1066f25f864Sjmcneill 	if (ap->ap_bus == b) {
1076f25f864Sjmcneill 		if (d > 0 || f > 0 || reg >= PCI_EXTCONF_SIZE) {
1086f25f864Sjmcneill 			*data = -1;
1096f25f864Sjmcneill 			return EINVAL;
1106f25f864Sjmcneill 		}
1116f25f864Sjmcneill 		*data = bus_space_read_4(ap->ap_bst, ap->ap_conf_bsh, reg);
1126f25f864Sjmcneill 		return 0;
1136f25f864Sjmcneill 	}
1146f25f864Sjmcneill 
1156f25f864Sjmcneill 	if (!acpi_pci_n1sdp_valid(pc, tag)) {
1166f25f864Sjmcneill 		*data = -1;
1176f25f864Sjmcneill 		return 0;
1186f25f864Sjmcneill 	}
1196f25f864Sjmcneill 
1206f25f864Sjmcneill 	return acpimcfg_conf_read(pc, tag, reg, data);
1216f25f864Sjmcneill }
1226f25f864Sjmcneill 
1236f25f864Sjmcneill static int
acpi_pci_n1sdp_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)1246f25f864Sjmcneill acpi_pci_n1sdp_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
1256f25f864Sjmcneill {
1266f25f864Sjmcneill 	struct acpi_pci_context *ap = pc->pc_conf_v;
1276f25f864Sjmcneill 	int b, d, f;
1286f25f864Sjmcneill 
1296f25f864Sjmcneill 	pci_decompose_tag(pc, tag, &b, &d, &f);
1306f25f864Sjmcneill 
1316f25f864Sjmcneill 	if (ap->ap_bus == b) {
1326f25f864Sjmcneill 		if (d > 0 || f > 0 || reg >= PCI_EXTCONF_SIZE) {
1336f25f864Sjmcneill 			return EINVAL;
1346f25f864Sjmcneill 		}
1356f25f864Sjmcneill 		bus_space_write_4(ap->ap_bst, ap->ap_conf_bsh, reg, data);
1366f25f864Sjmcneill 		return 0;
1376f25f864Sjmcneill 	}
1386f25f864Sjmcneill 
1396f25f864Sjmcneill 	if (!acpi_pci_n1sdp_valid(pc, tag))
1406f25f864Sjmcneill 		return 0;
1416f25f864Sjmcneill 
1426f25f864Sjmcneill 	return acpimcfg_conf_write(pc, tag, reg, data);
1436f25f864Sjmcneill }
1446f25f864Sjmcneill 
1456f25f864Sjmcneill void
acpi_pci_n1sdp_init(struct acpi_pci_context * ap)1466f25f864Sjmcneill acpi_pci_n1sdp_init(struct acpi_pci_context *ap)
1476f25f864Sjmcneill {
1486f25f864Sjmcneill 	bus_space_tag_t bst = &arm_generic_bs_tag;
1496f25f864Sjmcneill 	bus_space_handle_t bsh;
1506f25f864Sjmcneill 	paddr_t pa;
1516f25f864Sjmcneill 	int error;
1526f25f864Sjmcneill 	u_int n;
1536f25f864Sjmcneill 
1546f25f864Sjmcneill 	if (ap->ap_seg >= N1SDP_NSEGS)
1556f25f864Sjmcneill 		return;
1566f25f864Sjmcneill 
1576f25f864Sjmcneill 	if (n1sdp_data[ap->ap_seg] == NULL) {
1586f25f864Sjmcneill 		aprint_normal_dev(ap->ap_dev, "applying N1SDP quirk for segment %d\n", ap->ap_seg);
1596f25f864Sjmcneill 
1606f25f864Sjmcneill 		pa = N1SDP_SHARED_MEM_BASE + ap->ap_seg * N1SDP_TABLE_SIZE;
1616f25f864Sjmcneill 		if (bus_space_map(bst, pa, N1SDP_TABLE_SIZE, BUS_SPACE_MAP_LINEAR, &bsh) != 0)
1626f25f864Sjmcneill 			panic("acpi_pci_n1sdp_init: couldn't map PCIe discovery table");
1636f25f864Sjmcneill 
1646f25f864Sjmcneill 		n1sdp_data[ap->ap_seg] = bus_space_vaddr(bst, bsh);
1656f25f864Sjmcneill 		if (n1sdp_data[ap->ap_seg] == NULL)
1666f25f864Sjmcneill 			panic("acpi_pci_n1sdp_init: couldn't get PCIe discovery table VA");
1676f25f864Sjmcneill 
1686f25f864Sjmcneill 		error = bus_space_map(bst, n1sdp_data[ap->ap_seg]->rc_base_addr, PCI_EXTCONF_SIZE,
169*5158b98cSjmcneill 		    BUS_SPACE_MAP_NONPOSTED, &ap->ap_conf_bsh);
1706f25f864Sjmcneill 		if (error != 0)
1716f25f864Sjmcneill 			panic("acpi_pci_n1sdp_init: couldn't map segment %d", ap->ap_seg);
1726f25f864Sjmcneill 
1736f25f864Sjmcneill 		aprint_debug_dev(ap->ap_dev, "N1SDP: RC @ 0x%08x, %d devices\n",
1746f25f864Sjmcneill 		    n1sdp_data[ap->ap_seg]->rc_base_addr, n1sdp_data[ap->ap_seg]->nr_bdfs);
1756f25f864Sjmcneill 		for (n = 0; n < n1sdp_data[ap->ap_seg]->nr_bdfs; n++) {
176e4736b55Sjmcneill 			const uint32_t bdf = le32toh(n1sdp_data[ap->ap_seg]->valid_bdfs[n]);
1776f25f864Sjmcneill 			const int b = (bdf >> N1SDP_BUS_SHIFT) & 0xff;
1786f25f864Sjmcneill 			const int d = (bdf >> N1SDP_DEV_SHIFT) & 0x1f;
1796f25f864Sjmcneill 			const int f = (bdf >> N1SDP_FUNC_SHIFT) & 0x7;
1806f25f864Sjmcneill 			aprint_debug_dev(ap->ap_dev, "N1SDP: %02x:%02x.%x (%08x)\n", b, d, f, bdf);
1816f25f864Sjmcneill 		}
1826f25f864Sjmcneill 	}
1836f25f864Sjmcneill 
1846f25f864Sjmcneill 	ap->ap_conf_read = acpi_pci_n1sdp_conf_read;
1856f25f864Sjmcneill 	ap->ap_conf_write = acpi_pci_n1sdp_conf_write;
1866f25f864Sjmcneill 
187f264852aSjmcneill 	/* IO space access seems to cause async SErrors, so disable for now */
188f264852aSjmcneill 	ap->ap_pciflags_clear = PCI_FLAGS_IO_OKAY;
1896f25f864Sjmcneill }
190