1*26a64d43Schristos /* $NetBSD: ite_rt.c,v 1.25 2014/01/22 00:25:16 christos Exp $ */
2276eff6bSchopps
3e85a3c53Schopps /*
4e85a3c53Schopps * Copyright (c) 1993 Markus Wild
5e85a3c53Schopps * Copyright (c) 1993 Lutz Vieweg
6e85a3c53Schopps * All rights reserved.
7e85a3c53Schopps *
8e85a3c53Schopps * Redistribution and use in source and binary forms, with or without
9e85a3c53Schopps * modification, are permitted provided that the following conditions
10e85a3c53Schopps * are met:
11e85a3c53Schopps * 1. Redistributions of source code must retain the above copyright
12e85a3c53Schopps * notice, this list of conditions and the following disclaimer.
13e85a3c53Schopps * 2. Redistributions in binary form must reproduce the above copyright
14e85a3c53Schopps * notice, this list of conditions and the following disclaimer in the
15e85a3c53Schopps * documentation and/or other materials provided with the distribution.
16e85a3c53Schopps * 3. All advertising materials mentioning features or use of this software
17e85a3c53Schopps * must display the following acknowledgement:
18e85a3c53Schopps * This product includes software developed by Lutz Vieweg.
19e85a3c53Schopps * 4. The name of the author may not be used to endorse or promote products
20e85a3c53Schopps * derived from this software without specific prior written permission
21e85a3c53Schopps *
22e85a3c53Schopps * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23e85a3c53Schopps * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24e85a3c53Schopps * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25e85a3c53Schopps * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26e85a3c53Schopps * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27e85a3c53Schopps * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28e85a3c53Schopps * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29e85a3c53Schopps * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30e85a3c53Schopps * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31e85a3c53Schopps * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32e85a3c53Schopps */
331ea4df81Saymeric
341ea4df81Saymeric #include <sys/cdefs.h>
35*26a64d43Schristos __KERNEL_RCSID(0, "$NetBSD: ite_rt.c,v 1.25 2014/01/22 00:25:16 christos Exp $");
361ea4df81Saymeric
378c6621adSchopps #include "grfrt.h"
388c6621adSchopps #if NGRFRT > 0
398c6621adSchopps
407bb75ba6Schopps #include <sys/param.h>
417bb75ba6Schopps #include <sys/conf.h>
427bb75ba6Schopps #include <sys/proc.h>
4315d4cf6bSchopps #include <sys/device.h>
447bb75ba6Schopps #include <sys/ioctl.h>
457bb75ba6Schopps #include <sys/tty.h>
467bb75ba6Schopps #include <sys/systm.h>
4778bd633dSchopps #include <dev/cons.h>
487bb75ba6Schopps #include <machine/cpu.h>
4915d4cf6bSchopps #include <amiga/amiga/device.h>
5015d4cf6bSchopps #include <amiga/dev/itevar.h>
517bb75ba6Schopps #include <amiga/dev/grfioctl.h>
527bb75ba6Schopps #include <amiga/dev/grfvar.h>
537bb75ba6Schopps #include <amiga/dev/grf_rtreg.h>
54f208f367Smw
556484be3bSchopps int retina_console = 1;
5678bd633dSchopps
579382c873Saymeric void retina_cursor(struct ite_softc *, int);
589382c873Saymeric void retina_scroll(struct ite_softc *, int, int, int, int);
599382c873Saymeric void retina_deinit(struct ite_softc *);
609382c873Saymeric void retina_clear(struct ite_softc *, int, int, int, int);
619382c873Saymeric void retina_putc(struct ite_softc *, int, int, int, int);
629382c873Saymeric void retina_init(struct ite_softc *);
6315d4cf6bSchopps
64112379efSveego #ifdef RETINA_SPEED_HACK
659382c873Saymeric static void screen_up(struct ite_softc *, int, int, int);
669382c873Saymeric static void screen_down(struct ite_softc *, int, int, int);
67112379efSveego #endif
68112379efSveego
6978bd633dSchopps /*
7015d4cf6bSchopps * this function is called from grf_rt to init the grf_softc->g_conpri
7115d4cf6bSchopps * field each time a retina is attached.
7278bd633dSchopps */
7378bd633dSchopps int
grfrt_cnprobe(void)749382c873Saymeric grfrt_cnprobe(void)
7578bd633dSchopps {
7615d4cf6bSchopps static int done;
7715d4cf6bSchopps int rv;
7815d4cf6bSchopps
7915d4cf6bSchopps if (retina_console && done == 0)
8015d4cf6bSchopps rv = CN_INTERNAL;
816484be3bSchopps else
8215d4cf6bSchopps rv = CN_NORMAL;
8315d4cf6bSchopps done = 1;
8415d4cf6bSchopps return(rv);
8578bd633dSchopps }
8678bd633dSchopps
8715d4cf6bSchopps /*
8815d4cf6bSchopps * init the required fields in the grf_softc struct for a
8915d4cf6bSchopps * grf to function as an ite.
9015d4cf6bSchopps */
9115d4cf6bSchopps void
grfrt_iteinit(struct grf_softc * gp)929382c873Saymeric grfrt_iteinit(struct grf_softc *gp)
9315d4cf6bSchopps {
9415d4cf6bSchopps gp->g_iteinit = retina_init;
9515d4cf6bSchopps gp->g_itedeinit = retina_deinit;
9615d4cf6bSchopps gp->g_iteclear = retina_clear;
9715d4cf6bSchopps gp->g_iteputc = retina_putc;
9815d4cf6bSchopps gp->g_itescroll = retina_scroll;
9915d4cf6bSchopps gp->g_itecursor = retina_cursor;
10015d4cf6bSchopps }
10115d4cf6bSchopps
102112379efSveego
10315d4cf6bSchopps void
retina_init(struct ite_softc * ip)1049382c873Saymeric retina_init(struct ite_softc *ip)
105f208f367Smw {
106f208f367Smw struct MonDef *md;
107f208f367Smw
108b917a0d0Smw ip->priv = ip->grf->g_data;
109f208f367Smw md = (struct MonDef *) ip->priv;
110f208f367Smw
111f208f367Smw ip->cols = md->TX;
112f208f367Smw ip->rows = md->TY;
113f208f367Smw }
114f208f367Smw
115f208f367Smw
116112379efSveego void
retina_cursor(struct ite_softc * ip,int flag)1179382c873Saymeric retina_cursor(struct ite_softc *ip, int flag)
118f208f367Smw {
11953524e44Schristos volatile void *ba = ip->grf->g_regkva;
120f208f367Smw
121f208f367Smw if (flag == ERASE_CURSOR)
122f208f367Smw {
123f208f367Smw /* disable cursor */
124f208f367Smw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20);
125f208f367Smw }
126f208f367Smw else
127f208f367Smw {
128f208f367Smw int pos = ip->curx + ip->cury * ip->cols;
129f208f367Smw
130f208f367Smw /* make sure to enable cursor */
131f208f367Smw WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20);
132f208f367Smw
133f208f367Smw /* and position it */
134f208f367Smw WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8));
135f208f367Smw WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos);
136f208f367Smw
137f208f367Smw ip->cursorx = ip->curx;
138f208f367Smw ip->cursory = ip->cury;
139f208f367Smw }
140f208f367Smw }
141f208f367Smw
142f208f367Smw
143f208f367Smw
144112379efSveego #ifdef RETINA_SPEED_HACK
145112379efSveego static void
screen_up(struct ite_softc * ip,int top,int bottom,int lines)1469382c873Saymeric screen_up(struct ite_softc *ip, int top, int bottom, int lines)
147f208f367Smw {
14853524e44Schristos volatile void *ba = ip->grf->g_regkva;
14953524e44Schristos volatile void *fb = ip->grf->g_fbkva;
150f208f367Smw const struct MonDef * md = (struct MonDef *) ip->priv;
151f208f367Smw
152f208f367Smw /* do some bounds-checking here.. */
153f208f367Smw if (top >= bottom)
154f208f367Smw return;
155f208f367Smw
156f208f367Smw if (top + lines >= bottom)
157f208f367Smw {
158f208f367Smw retina_clear (ip, top, 0, bottom - top, ip->cols);
159f208f367Smw return;
160f208f367Smw }
161f208f367Smw
162f208f367Smw /* the trick here is to use a feature of the NCR chip. It can
163f208f367Smw optimize data access in various read/write modes. One of
164f208f367Smw the modes is able to read/write from/to different zones.
165f208f367Smw
166f208f367Smw Thus, by setting the read-offset to lineN, and the write-offset
167f208f367Smw to line0, we just cause read/write cycles for all characters
168f208f367Smw up to the last line, and have the chip transfer the data. The
169f208f367Smw `addqb' are the cheapest way to cause read/write cycles (DONT
170f208f367Smw use `tas' on the Amiga!), their results are completely ignored
171f208f367Smw by the NCR chip, it just replicates what it just read. */
172f208f367Smw
173f208f367Smw /* write to primary, read from secondary */
174112379efSveego WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
175112379efSveego (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
176f208f367Smw /* clear extended chain4 mode */
177f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
178f208f367Smw
179f208f367Smw /* set write mode 1, "[...] data in the read latches is written
180f208f367Smw to memory during CPU memory write cycles. [...]" */
181112379efSveego WGfx (ba, GCT_ID_GRAPHICS_MODE,
182112379efSveego (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
183f208f367Smw
184f208f367Smw {
185f208f367Smw /* write to line TOP */
186f208f367Smw long toploc = top * (md->TX / 16);
187f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc));
188f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8)));
189f208f367Smw }
190f208f367Smw {
191f208f367Smw /* read from line TOP + LINES */
192f208f367Smw long fromloc = (top+lines) * (md->TX / 16);
193f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ;
194f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
195f208f367Smw }
196f208f367Smw {
19753524e44Schristos void *p = (void *)fb;
198f208f367Smw /* transfer all characters but LINES lines, unroll by 16 */
199f208f367Smw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
200f208f367Smw do {
2012d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2022d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2032d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2042d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2052d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2062d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2072d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2082d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2092d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2102d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2112d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2122d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2132d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2142d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2152d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
2162d65de24Sperry __asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
217f208f367Smw } while (x--);
218f208f367Smw }
219f208f367Smw
220f208f367Smw /* reset to default values */
221f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
222f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
223f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
224f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
225f208f367Smw /* write mode 0 */
226112379efSveego WGfx (ba, GCT_ID_GRAPHICS_MODE,
227112379efSveego (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
228f208f367Smw /* extended chain4 enable */
229112379efSveego WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR,
230112379efSveego RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
231f208f367Smw /* read/write to primary on A0, secondary on B0 */
232112379efSveego WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
233112379efSveego (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40);
234f208f367Smw
235f208f367Smw
236f208f367Smw /* fill the free lines with spaces */
237f208f367Smw
238f208f367Smw { /* feed latches with value */
239f208f367Smw unsigned short * f = (unsigned short *) fb;
240f208f367Smw
241f208f367Smw f += (1 + bottom - lines) * md->TX * 2;
242f208f367Smw *f = 0x2010;
243f208f367Smw }
244f208f367Smw
245f208f367Smw /* clear extended chain4 mode */
246f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
247f208f367Smw /* set write mode 1, "[...] data in the read latches is written
248f208f367Smw to memory during CPU memory write cycles. [...]" */
249f208f367Smw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
250f208f367Smw
251f208f367Smw {
252f208f367Smw unsigned long * p = (unsigned long *) fb;
253f208f367Smw short x = (lines * (md->TX/16)) - 1;
254f208f367Smw const unsigned long dummyval = 0;
255f208f367Smw
256f208f367Smw p += (1 + bottom - lines) * (md->TX/4);
257f208f367Smw
258f208f367Smw do {
259f208f367Smw *p++ = dummyval;
260f208f367Smw *p++ = dummyval;
261f208f367Smw *p++ = dummyval;
262f208f367Smw *p++ = dummyval;
263f208f367Smw } while (x--);
264f208f367Smw }
265f208f367Smw
266f208f367Smw /* write mode 0 */
267f208f367Smw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
268f208f367Smw /* extended chain4 enable */
269f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
270f208f367Smw };
271f208f367Smw
272112379efSveego
273112379efSveego static void
screen_down(struct ite_softc * ip,int top,int bottom,int lines)2749382c873Saymeric screen_down(struct ite_softc *ip, int top, int bottom, int lines)
275f208f367Smw {
27653524e44Schristos volatile void *ba = ip->grf->g_regkva;
27753524e44Schristos volatile void *fb = ip->grf->g_fbkva;
278f208f367Smw const struct MonDef * md = (struct MonDef *) ip->priv;
279f208f367Smw
280f208f367Smw /* do some bounds-checking here.. */
281f208f367Smw if (top >= bottom)
282f208f367Smw return;
283f208f367Smw
284f208f367Smw if (top + lines >= bottom)
285f208f367Smw {
286f208f367Smw retina_clear (ip, top, 0, bottom - top, ip->cols);
287f208f367Smw return;
288f208f367Smw }
289f208f367Smw
290f208f367Smw /* see screen_up() for explanation of chip-tricks */
291f208f367Smw
292f208f367Smw /* write to primary, read from secondary */
293112379efSveego WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
294112379efSveego (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
295f208f367Smw /* clear extended chain4 mode */
296f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
297f208f367Smw
298f208f367Smw /* set write mode 1, "[...] data in the read latches is written
299f208f367Smw to memory during CPU memory write cycles. [...]" */
300f208f367Smw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
301f208f367Smw
302f208f367Smw {
303f208f367Smw /* write to line TOP + LINES */
304f208f367Smw long toloc = (top + lines) * (md->TX / 16);
305f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc));
306f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8)));
307f208f367Smw }
308f208f367Smw {
309f208f367Smw /* read from line TOP */
310f208f367Smw long fromloc = top * (md->TX / 16);
311f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc));
312f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
313f208f367Smw }
314f208f367Smw
315f208f367Smw {
31653524e44Schristos void *p = (void *)fb;
317f208f367Smw short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
318f208f367Smw p += (1 + bottom - (top + lines)) * md->TX;
319f208f367Smw do {
3202d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3212d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3222d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3232d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3242d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3252d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3262d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3272d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3282d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3292d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3302d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3312d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3322d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3332d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3342d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
3352d65de24Sperry __asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
336f208f367Smw } while (x--);
337f208f367Smw }
338f208f367Smw
339f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
340f208f367Smw WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
341f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
342f208f367Smw WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
343f208f367Smw
344f208f367Smw /* write mode 0 */
345112379efSveego WGfx (ba, GCT_ID_GRAPHICS_MODE,
346112379efSveego (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
347f208f367Smw /* extended chain4 enable */
348f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
349f208f367Smw /* read/write to primary on A0, secondary on B0 */
350112379efSveego WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA,
351112379efSveego (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 );
352f208f367Smw
353f208f367Smw /* fill the free lines with spaces */
354f208f367Smw
355f208f367Smw { /* feed latches with value */
356f208f367Smw unsigned short * f = (unsigned short *) fb;
357f208f367Smw
358f208f367Smw f += top * md->TX * 2;
359f208f367Smw *f = 0x2010;
360f208f367Smw }
361f208f367Smw
362f208f367Smw /* clear extended chain4 mode */
363f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
364f208f367Smw /* set write mode 1, "[...] data in the read latches is written
365f208f367Smw to memory during CPU memory write cycles. [...]" */
366f208f367Smw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
367f208f367Smw
368f208f367Smw {
369f208f367Smw unsigned long * p = (unsigned long *) fb;
370f208f367Smw short x = (lines * (md->TX/16)) - 1;
371f208f367Smw const unsigned long dummyval = 0;
372f208f367Smw
373f208f367Smw p += top * (md->TX/4);
374f208f367Smw
375f208f367Smw do {
376f208f367Smw *p++ = dummyval;
377f208f367Smw *p++ = dummyval;
378f208f367Smw *p++ = dummyval;
379f208f367Smw *p++ = dummyval;
380f208f367Smw } while (x--);
381f208f367Smw }
382f208f367Smw
383f208f367Smw /* write mode 0 */
384f208f367Smw WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
385f208f367Smw /* extended chain4 enable */
386f208f367Smw WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
387f208f367Smw };
388112379efSveego #endif /* RETINA_SPEED_HACK */
389f208f367Smw
390112379efSveego
391112379efSveego void
retina_deinit(struct ite_softc * ip)3929382c873Saymeric retina_deinit(struct ite_softc *ip)
393f208f367Smw {
394f208f367Smw ip->flags &= ~ITE_INITED;
395f208f367Smw }
396f208f367Smw
397f208f367Smw
398112379efSveego void
retina_putc(struct ite_softc * ip,int c,int dy,int dx,int mode)3999382c873Saymeric retina_putc(struct ite_softc *ip, int c, int dy, int dx, int mode)
400f208f367Smw {
4013ba91b05She volatile char *fb = (volatile char*)ip->grf->g_fbkva;
402f208f367Smw register u_char attr;
403f208f367Smw
404f208f367Smw attr = (mode & ATTR_INV) ? 0x21 : 0x10;
405f208f367Smw if (mode & ATTR_UL) attr = 0x01; /* ???????? */
406f208f367Smw if (mode & ATTR_BOLD) attr |= 0x08;
407f208f367Smw if (mode & ATTR_BLINK) attr |= 0x80;
408f208f367Smw
409f208f367Smw fb += 4 * (dy * ip->cols + dx);
410f208f367Smw *fb++ = c; *fb = attr;
411f208f367Smw }
412f208f367Smw
413112379efSveego
414112379efSveego void
retina_clear(struct ite_softc * ip,int sy,int sx,int h,int w)4159382c873Saymeric retina_clear(struct ite_softc *ip, int sy, int sx, int h, int w)
416f208f367Smw {
4173ba91b05She volatile u_short * fb = (volatile u_short *) ip->grf->g_fbkva;
418f208f367Smw short x;
419f208f367Smw const u_short fillval = 0x2010;
420112379efSveego
421f208f367Smw /* could probably be optimized just like the scrolling functions !! */
422f208f367Smw fb += 2 * (sy * ip->cols + sx);
423f208f367Smw while (h--)
424f208f367Smw {
425f208f367Smw for (x = 2 * (w - 1); x >= 0; x -= 2)
426f208f367Smw fb[x] = fillval;
427f208f367Smw fb += 2 * ip->cols;
428f208f367Smw }
429f208f367Smw }
430f208f367Smw
431112379efSveego
43279bf8f86Schopps /*
43379bf8f86Schopps * RETINA_SPEED_HACK code seems to work on some boards and on others
43479bf8f86Schopps * it causes text to smear horizontally
43579bf8f86Schopps */
43679bf8f86Schopps void
retina_scroll(struct ite_softc * ip,int sy,int sx,int count,int dir)4379382c873Saymeric retina_scroll(struct ite_softc *ip, int sy, int sx, int count, int dir)
438f208f367Smw {
43979bf8f86Schopps u_long *fb;
44079bf8f86Schopps
4413ba91b05She fb = (u_long *)__UNVOLATILE(ip->grf->g_fbkva);
442f208f367Smw
443f208f367Smw retina_cursor(ip, ERASE_CURSOR);
444f208f367Smw
44579bf8f86Schopps if (dir == SCROLL_UP) {
44679bf8f86Schopps #ifdef RETINA_SPEED_HACK
447f208f367Smw screen_up(ip, sy - count, ip->bottom_margin, count);
44879bf8f86Schopps #else
449e2cb8590Scegger memcpy(fb + (sy - count) * ip->cols, fb + sy * ip->cols,
45079bf8f86Schopps 4 * (ip->bottom_margin - sy + 1) * ip->cols);
45179bf8f86Schopps retina_clear(ip, ip->bottom_margin + 1 - count, 0, count,
45279bf8f86Schopps ip->cols);
45379bf8f86Schopps #endif
45479bf8f86Schopps } else if (dir == SCROLL_DOWN) {
45579bf8f86Schopps #ifdef RETINA_SPEED_HACK
456f208f367Smw screen_down(ip, sy, ip->bottom_margin, count);
45779bf8f86Schopps #else
458e2cb8590Scegger memcpy(fb + (sy + count) * ip->cols, fb + sy * ip->cols,
45979bf8f86Schopps 4 * (ip->bottom_margin - sy - count + 1) * ip->cols);
46079bf8f86Schopps retina_clear(ip, sy, 0, count, ip->cols);
461967e7d4fSchopps #endif
46279bf8f86Schopps } else if (dir == SCROLL_RIGHT) {
463e2cb8590Scegger memcpy(fb + sx + sy * ip->cols + count, fb + sx + sy * ip->cols,
46479bf8f86Schopps 4 * (ip->cols - (sx + count)));
465f208f367Smw retina_clear(ip, sy, sx, 1, count);
46679bf8f86Schopps } else {
467e2cb8590Scegger memcpy(fb + sx - count + sy * ip->cols, fb + sx + sy * ip->cols,
46879bf8f86Schopps 4 * (ip->cols - sx));
469f208f367Smw retina_clear(ip, sy, ip->cols - count, 1, count);
470f208f367Smw }
47179bf8f86Schopps #ifndef RETINA_SPEED_HACK
47279bf8f86Schopps retina_cursor(ip, !ERASE_CURSOR);
47379bf8f86Schopps #endif
474f208f367Smw }
4758c6621adSchopps
4768c6621adSchopps #endif /* NGRFRT */
477