1*eacc5f97Smatt /* $NetBSD: logout.h,v 1.8 2012/02/06 02:14:13 matt Exp $ */ 2dfe345a4Smjacob 3dfe345a4Smjacob /* 4dfe345a4Smjacob * Copyright (c) 1998 by Matthew Jacob 5dfe345a4Smjacob * NASA AMES Research Center. 6dfe345a4Smjacob * All rights reserved. 7dfe345a4Smjacob * 8dfe345a4Smjacob * Redistribution and use in source and binary forms, with or without 9dfe345a4Smjacob * modification, are permitted provided that the following conditions 10dfe345a4Smjacob * are met: 11dfe345a4Smjacob * 1. Redistributions of source code must retain the above copyright 12dfe345a4Smjacob * notice immediately at the beginning of the file, without modification, 13dfe345a4Smjacob * this list of conditions, and the following disclaimer. 14dfe345a4Smjacob * 2. Redistributions in binary form must reproduce the above copyright 15dfe345a4Smjacob * notice, this list of conditions and the following disclaimer in the 16dfe345a4Smjacob * documentation and/or other materials provided with the distribution. 17dfe345a4Smjacob * 3. The name of the author may not be used to endorse or promote products 18dfe345a4Smjacob * derived from this software without specific prior written permission. 19dfe345a4Smjacob * 20dfe345a4Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21dfe345a4Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22dfe345a4Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23dfe345a4Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24dfe345a4Smjacob * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25dfe345a4Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26dfe345a4Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27dfe345a4Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28dfe345a4Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29dfe345a4Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30dfe345a4Smjacob * SUCH DAMAGE. 31dfe345a4Smjacob */ 32dfe345a4Smjacob 33dfe345a4Smjacob /* 34b1c7ac0eSwiz * Various Alpha OSF/1 PAL Logout error definitions. 35dfe345a4Smjacob */ 36dfe345a4Smjacob 37dfe345a4Smjacob /* 38a45ca84aSnathanw * Information gathered from: DEC documentation 39a45ca84aSnathanw */ 40a45ca84aSnathanw 41a45ca84aSnathanw /* 42a45ca84aSnathanw * Avanti (AlphaStation 200 and 400) Specific PALcode Exception Logout 43a45ca84aSnathanw * Area Definitions 44a45ca84aSnathanw */ 45a45ca84aSnathanw 46a45ca84aSnathanw /* 47a45ca84aSnathanw * Avanti Specific common logout frame header. 48a45ca84aSnathanw * *Almost* identical to the generic logout header listed in alpha_cpu.h. 49a45ca84aSnathanw */ 50a45ca84aSnathanw 51a45ca84aSnathanw typedef struct { 52a45ca84aSnathanw unsigned int la_frame_size; /* frame size */ 53a45ca84aSnathanw unsigned int la_flags; /* flags; see alpha_cpu.h */ 54d20841bbSwiz unsigned int la_cpu_offset; /* offset to CPU area */ 55a45ca84aSnathanw unsigned int la_system_offset; /* offset to system area */ 56a45ca84aSnathanw unsigned long mcheck_code; /* machine check code */ 57a45ca84aSnathanw } mc_hdr_avanti; 58a45ca84aSnathanw 59a45ca84aSnathanw /* Machine Check Codes */ 60a45ca84aSnathanw 61a45ca84aSnathanw /* SCB 660 Fatal Machine Checks */ 62a45ca84aSnathanw #define AVANTI_RETRY_TIMEOUT 0x201L 63a45ca84aSnathanw #define AVANTI_DMA_DATA_PARITY 0x202L 64a45ca84aSnathanw #define AVANTI_IO_PARITY 0x203L 65a45ca84aSnathanw #define AVANTI_TARGET_ABORT 0x204L 66a45ca84aSnathanw #define AVANTI_NO_DEVICE 0x205L 67a45ca84aSnathanw #define AVANTI_CORRRECTABLE_MEMORY 0x206L /* Should never occur */ 68a45ca84aSnathanw #define AVANTI_UNCORRECTABLE_PCI_MEMORY 0x207L 69a45ca84aSnathanw #define AVANTI_INVALID_PT_LOOKUP 0x208L 70a45ca84aSnathanw #define AVANTI_MEMORY 0x209L 71a45ca84aSnathanw #define AVANTI_BCACHE_TAG_ADDR_PARITY 0x20AL 72a45ca84aSnathanw #define AVANTI_BCACHE_TAG_CTRL_PARITY 0x20BL 73a45ca84aSnathanw #define AVANTI_NONEXISTENT_MEMORY 0x20CL 74a45ca84aSnathanw #define AVANTI_IO_BUS 0x20DL 75a45ca84aSnathanw #define AVANTI_BCACHE_TAG_PARITY 0x80L 76a45ca84aSnathanw #define AVANTI_BCACHE_TAG_CTRL_PARITY2 0x82L 77a45ca84aSnathanw 78a45ca84aSnathanw /* SCB 670 Processor Fatal Machine Checks */ 79a45ca84aSnathanw #define AVANTI_HARD_ERROR 0x84L 80a45ca84aSnathanw #define AVANTI_CORRECTABLE_ECC 0x86L 81a45ca84aSnathanw #define AVANTI_NONCORRECTABLE_ECC 0x88L 82a45ca84aSnathanw #define AVANTI_UNKNOWN_ERROR 0x8AL 83a45ca84aSnathanw #define AVANTI_SOFT_ERROR 0x8CL 84a45ca84aSnathanw #define AVANTI_BUGCHECK 0x8EL 85a45ca84aSnathanw #define AVANTI_OS_BUGCHECK 0x90L 86a45ca84aSnathanw #define AVANTI_DCACHE_FILL_PARITY 0x92L 87a45ca84aSnathanw #define AVANTI_ICACHE_FILL_PARITY 0x94L 88a45ca84aSnathanw 89a45ca84aSnathanw typedef struct { 90a45ca84aSnathanw /* Registers from the CPU */ 91*eacc5f97Smatt uint64_t paltemp[32]; /* PAL TEMP REGS. */ 92*eacc5f97Smatt uint64_t exc_addr; /* Address of excepting ins. */ 93*eacc5f97Smatt uint64_t exc_sum; /* Summary of arithmetic traps. */ 94*eacc5f97Smatt uint64_t exc_mask; /* Exception mask. */ 95*eacc5f97Smatt uint64_t iccsr; 96*eacc5f97Smatt uint64_t pal_base; /* Base address for PALcode. */ 97*eacc5f97Smatt uint64_t hier; 98*eacc5f97Smatt uint64_t hirr; 99*eacc5f97Smatt uint64_t mm_csr; 100*eacc5f97Smatt uint64_t dc_stat; 101*eacc5f97Smatt uint64_t dc_addr; 102*eacc5f97Smatt uint64_t abox_ctl; 103*eacc5f97Smatt uint64_t biu_stat; /* Bus Interface Unit Status. */ 104*eacc5f97Smatt uint64_t biu_addr; 105*eacc5f97Smatt uint64_t biu_ctl; 106*eacc5f97Smatt uint64_t fill_syndrome; 107*eacc5f97Smatt uint64_t fill_addr; 108*eacc5f97Smatt uint64_t va; 109*eacc5f97Smatt uint64_t bc_tag; 110a45ca84aSnathanw 111a45ca84aSnathanw /* Registers from the cache and memory controller (21071-CA) */ 112*eacc5f97Smatt uint64_t coma_gcr; /* Error and Diag. Status. */ 113*eacc5f97Smatt uint64_t coma_edsr; 114*eacc5f97Smatt uint64_t coma_ter; 115*eacc5f97Smatt uint64_t coma_elar; 116*eacc5f97Smatt uint64_t coma_ehar; 117*eacc5f97Smatt uint64_t coma_ldlr; 118*eacc5f97Smatt uint64_t coma_ldhr; 119*eacc5f97Smatt uint64_t coma_base0; 120*eacc5f97Smatt uint64_t coma_base1; 121*eacc5f97Smatt uint64_t coma_base2; 122*eacc5f97Smatt uint64_t coma_cnfg0; 123*eacc5f97Smatt uint64_t coma_cnfg1; 124*eacc5f97Smatt uint64_t coma_cnfg2; 125a45ca84aSnathanw 126a45ca84aSnathanw /* Registers from the PCI bridge (21071-DA) */ 127*eacc5f97Smatt uint64_t epic_dcsr; /* Diag. Control and Status. */ 128*eacc5f97Smatt uint64_t epic_pear; 129*eacc5f97Smatt uint64_t epic_sear; 130*eacc5f97Smatt uint64_t epic_tbr1; 131*eacc5f97Smatt uint64_t epic_tbr2; 132*eacc5f97Smatt uint64_t epic_pbr1; 133*eacc5f97Smatt uint64_t epic_pbr2; 134*eacc5f97Smatt uint64_t epic_pmr1; 135*eacc5f97Smatt uint64_t epic_pmr2; 136*eacc5f97Smatt uint64_t epic_harx1; 137*eacc5f97Smatt uint64_t epic_harx2; 138*eacc5f97Smatt uint64_t epic_pmlt; 139*eacc5f97Smatt uint64_t epic_tag0; 140*eacc5f97Smatt uint64_t epic_tag1; 141*eacc5f97Smatt uint64_t epic_tag2; 142*eacc5f97Smatt uint64_t epic_tag3; 143*eacc5f97Smatt uint64_t epic_tag4; 144*eacc5f97Smatt uint64_t epic_tag5; 145*eacc5f97Smatt uint64_t epic_tag6; 146*eacc5f97Smatt uint64_t epic_tag7; 147*eacc5f97Smatt uint64_t epic_data0; 148*eacc5f97Smatt uint64_t epic_data1; 149*eacc5f97Smatt uint64_t epic_data2; 150*eacc5f97Smatt uint64_t epic_data3; 151*eacc5f97Smatt uint64_t epic_data4; 152*eacc5f97Smatt uint64_t epic_data5; 153*eacc5f97Smatt uint64_t epic_data6; 154*eacc5f97Smatt uint64_t epic_data7; 155a45ca84aSnathanw } mc_uc_avanti; 156a45ca84aSnathanw 157a45ca84aSnathanw /* 158dfe345a4Smjacob * Information gathered from: OSF/1 header files. 159dfe345a4Smjacob */ 160dfe345a4Smjacob 161dfe345a4Smjacob 162dfe345a4Smjacob /* 163dfe345a4Smjacob * EV5 Specific OSF/1 Pal Code Exception Logout Area Definitions 164dfe345a4Smjacob * (inspired from OSF/1 Header files). 165dfe345a4Smjacob */ 166dfe345a4Smjacob 167dfe345a4Smjacob /* 168dfe345a4Smjacob * EV5 Specific common logout frame header. 169dfe345a4Smjacob * *Almost* identical to the generic logout header listed in alpha_cpu.h. 170dfe345a4Smjacob */ 171dfe345a4Smjacob 172dfe345a4Smjacob typedef struct { 173dfe345a4Smjacob unsigned int la_frame_size; /* frame size */ 174dfe345a4Smjacob unsigned int la_flags; /* flags; see alpha_cpu.h */ 175d20841bbSwiz unsigned int la_cpu_offset; /* offset to CPU area */ 176dfe345a4Smjacob unsigned int la_system_offset; /* offset to system area */ 177dfe345a4Smjacob unsigned long mcheck_code; /* machine check code */ 178dfe345a4Smjacob } mc_hdr_ev5; 179dfe345a4Smjacob 180dfe345a4Smjacob /* Machine Check Codes */ 181dfe345a4Smjacob #define EV5_CORRECTED 0x86L 182dfe345a4Smjacob #define SYSTEM_CORRECTED 0x201L 183dfe345a4Smjacob 184dfe345a4Smjacob /* 185dfe345a4Smjacob * EV5 Specific Machine Check logout frame for uncorrectable errors. 186dfe345a4Smjacob * This is used to log uncorrectable errors such as double bit ECC errors. 187dfe345a4Smjacob * 188d20841bbSwiz * This typically resides in the CPU offset area of the logout frame. 189dfe345a4Smjacob */ 190dfe345a4Smjacob 191dfe345a4Smjacob typedef struct { 192*eacc5f97Smatt uint64_t shadow[8]; /* Shadow reg. 8-14, 25 */ 193*eacc5f97Smatt uint64_t paltemp[24]; /* PAL TEMP REGS. */ 194*eacc5f97Smatt uint64_t exc_addr; /* Address of excepting ins. */ 195*eacc5f97Smatt uint64_t exc_sum; /* Summary of arithmetic traps. */ 196*eacc5f97Smatt uint64_t exc_mask; /* Exception mask. */ 197*eacc5f97Smatt uint64_t pal_base; /* Base address for PALcode. */ 198*eacc5f97Smatt uint64_t isr; /* Interrupt Status Reg. */ 199*eacc5f97Smatt uint64_t icsr; /* CURRENT SETUP OF EV5 IBOX */ 200*eacc5f97Smatt uint64_t ic_perr_stat; /* 201dfe345a4Smjacob * I-CACHE Reg: 202dfe345a4Smjacob * <13> IBOX Timeout 203dfe345a4Smjacob * <12> TAG parity 204dfe345a4Smjacob * <11> Data parity 205dfe345a4Smjacob */ 206*eacc5f97Smatt uint64_t dc_perr_stat; /* D-CACHE error Reg: 207dfe345a4Smjacob * Bits set to 1: 208dfe345a4Smjacob * <2> Data error in bank 0 209dfe345a4Smjacob * <3> Data error in bank 1 210dfe345a4Smjacob * <4> Tag error in bank 0 211dfe345a4Smjacob * <5> Tag error in bank 1 212dfe345a4Smjacob */ 213*eacc5f97Smatt uint64_t va; /* Effective VA of fault or miss. */ 214*eacc5f97Smatt uint64_t mm_stat; /* 215dfe345a4Smjacob * Holds the reason for D-stream 216dfe345a4Smjacob * fault or D-cache parity errors 217dfe345a4Smjacob */ 218*eacc5f97Smatt uint64_t sc_addr; /* 219dfe345a4Smjacob * Address that was being accessed 220dfe345a4Smjacob * when EV5 detected Secondary cache 221dfe345a4Smjacob * failure. 222dfe345a4Smjacob */ 223*eacc5f97Smatt uint64_t sc_stat; /* 224dfe345a4Smjacob * Helps determine if the error was 225dfe345a4Smjacob * TAG/Data parity(Secondary Cache) 226dfe345a4Smjacob */ 227*eacc5f97Smatt uint64_t bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ 228*eacc5f97Smatt uint64_t ei_addr; /* 229dfe345a4Smjacob * Physical address of any transfer 230dfe345a4Smjacob * that is logged in the EV5 EI_STAT 231dfe345a4Smjacob */ 232*eacc5f97Smatt uint64_t fill_syndrome; /* For correcting ECC errors. */ 233*eacc5f97Smatt uint64_t ei_stat; /* 234dfe345a4Smjacob * Helps identify reason of any 235dfe345a4Smjacob * processor uncorrectable error 236dfe345a4Smjacob * at its external interface. 237dfe345a4Smjacob */ 238*eacc5f97Smatt uint64_t ld_lock; /* Contents of EV5 LD_LOCK register*/ 239dfe345a4Smjacob } mc_uc_ev5; 240dfe345a4Smjacob #define EV5_IC_PERR_IBOXTMO 0x2000 241dfe345a4Smjacob 242dfe345a4Smjacob /* 243dfe345a4Smjacob * EV5 Specific Machine Check logout frame for correctable errors. 244dfe345a4Smjacob * 245dfe345a4Smjacob * This is used to log correctable errors such as Single bit ECC errors. 246dfe345a4Smjacob */ 247dfe345a4Smjacob typedef struct { 248*eacc5f97Smatt uint64_t ei_addr; /* 249dfe345a4Smjacob * Physical address of any transfer 250dfe345a4Smjacob * that is logged in the EV5 EI_STAT 251dfe345a4Smjacob */ 252*eacc5f97Smatt uint64_t fill_syndrome; /* For correcting ECC errors. */ 253*eacc5f97Smatt uint64_t ei_stat; /* 254dfe345a4Smjacob * Helps identify reason of any 255dfe345a4Smjacob * processor uncorrectable error 256dfe345a4Smjacob * at its external interface. 257dfe345a4Smjacob */ 258*eacc5f97Smatt uint64_t isr; /* Interrupt Status Reg. */ 259dfe345a4Smjacob } mc_cc_ev5; 260dfe345a4Smjacob 261dfe345a4Smjacob 262dfe345a4Smjacob #ifdef _KERNEL 26381afcb39Sthorpej extern void ev5_logout_print(mc_hdr_ev5 *, mc_uc_ev5 *); 264dfe345a4Smjacob #endif 2659fb47a82Shans 2669fb47a82Shans /* 2679fb47a82Shans * EV6/67 specific Machine Check logout definitions 2689fb47a82Shans * from DS20E Service Guide, EK-K8F6W-SV. A01 2699fb47a82Shans */ 2709fb47a82Shans 2719fb47a82Shans struct ev6_logout_area { 2729fb47a82Shans struct alpha_logout_area la; 2739fb47a82Shans uint32_t mchk_code; 2749fb47a82Shans uint32_t mchk_rev; 2759fb47a82Shans }; 2769fb47a82Shans 2779fb47a82Shans struct ev6_logout_proc { 2789fb47a82Shans uint64_t i_stat; 2799fb47a82Shans uint64_t dc_stat; 2809fb47a82Shans uint64_t c_addr; 2819fb47a82Shans uint64_t c_syndrome1; 2829fb47a82Shans uint64_t c_syndrome0; 2839fb47a82Shans uint64_t c_stat; 2849fb47a82Shans uint64_t c_sts; 2859fb47a82Shans uint64_t mm_stat; 2869fb47a82Shans uint64_t exc_addr; 2879fb47a82Shans uint64_t ier_cm; 2889fb47a82Shans uint64_t isum; 2899fb47a82Shans uint64_t _r; 2909fb47a82Shans uint64_t pal_base; 2919fb47a82Shans uint64_t i_ctl; 2929fb47a82Shans uint64_t pctx; 2939fb47a82Shans }; 2949fb47a82Shans 2959fb47a82Shans struct ev6_logout_sys { 2969fb47a82Shans uint64_t flags; 2979fb47a82Shans uint64_t dir; 2989fb47a82Shans uint64_t misc; 2999fb47a82Shans uint64_t p0_error; 3009fb47a82Shans uint64_t p1_error; 3019fb47a82Shans }; 3029fb47a82Shans 303