1*7d4a1addSreinoud /* $NetBSD: rapidereg.h,v 1.1 2001/10/05 22:27:58 reinoud Exp $ */ 2*7d4a1addSreinoud 3*7d4a1addSreinoud /* 4*7d4a1addSreinoud * Copyright (c) 1997 Mark Brinicombe 5*7d4a1addSreinoud * Copyright (c) 1997 Causality Limited 6*7d4a1addSreinoud * 7*7d4a1addSreinoud * Redistribution and use in source and binary forms, with or without 8*7d4a1addSreinoud * modification, are permitted provided that the following conditions 9*7d4a1addSreinoud * are met: 10*7d4a1addSreinoud * 1. Redistributions of source code must retain the above copyright 11*7d4a1addSreinoud * notice, this list of conditions and the following disclaimer. 12*7d4a1addSreinoud * 2. Redistributions in binary form must reproduce the above copyright 13*7d4a1addSreinoud * notice, this list of conditions and the following disclaimer in the 14*7d4a1addSreinoud * documentation and/or other materials provided with the distribution. 15*7d4a1addSreinoud * 3. All advertising materials mentioning features or use of this software 16*7d4a1addSreinoud * must display the following acknowledgement: 17*7d4a1addSreinoud * This product includes software developed by Mark Brinicombe 18*7d4a1addSreinoud * for the NetBSD Project. 19*7d4a1addSreinoud * 4. The name of the author may not be used to endorse or promote products 20*7d4a1addSreinoud * derived from this software without specific prior written permission. 21*7d4a1addSreinoud * 22*7d4a1addSreinoud * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23*7d4a1addSreinoud * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24*7d4a1addSreinoud * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25*7d4a1addSreinoud * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26*7d4a1addSreinoud * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27*7d4a1addSreinoud * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28*7d4a1addSreinoud * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29*7d4a1addSreinoud * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30*7d4a1addSreinoud * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31*7d4a1addSreinoud * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*7d4a1addSreinoud */ 33*7d4a1addSreinoud 34*7d4a1addSreinoud /* 35*7d4a1addSreinoud * Thanks to Chris Honey at Raymond Datalink for providing information on 36*7d4a1addSreinoud * addressing the RapIDE podule. 37*7d4a1addSreinoud * RapIDE32 is Copyright (C) 1995,1996 Raymond Datalink. RapIDE32 is 38*7d4a1addSreinoud * manufactured under license by Yellowstone Educational Solutions. 39*7d4a1addSreinoud */ 40*7d4a1addSreinoud 41*7d4a1addSreinoud /* 42*7d4a1addSreinoud * Registers and address offsets for the Yellowstone RapIDE card. 43*7d4a1addSreinoud * 44*7d4a1addSreinoud * These are for issue 2 cards only. 45*7d4a1addSreinoud */ 46*7d4a1addSreinoud 47*7d4a1addSreinoud /* 48*7d4a1addSreinoud * This file needs to be extended to provide register information on 49*7d4a1addSreinoud * both versions of the card. 50*7d4a1addSreinoud */ 51*7d4a1addSreinoud 52*7d4a1addSreinoud /* IDE drive registers */ 53*7d4a1addSreinoud 54*7d4a1addSreinoud #define PRIMARY_DRIVE_REGISTERS_OFFSET 0x400080 55*7d4a1addSreinoud #define PRIMARY_AUX_REGISTER_OFFSET 0x400298 56*7d4a1addSreinoud #define PRIMARY_DATA_REGISTER_OFFSET 0x600080 57*7d4a1addSreinoud 58*7d4a1addSreinoud #define SECONDARY_DRIVE_REGISTERS_OFFSET 0x400000 59*7d4a1addSreinoud #define SECONDARY_AUX_REGISTER_OFFSET 0x400218 60*7d4a1addSreinoud #define SECONDARY_DATA_REGISTER_OFFSET 0x600000 61*7d4a1addSreinoud 62*7d4a1addSreinoud #define DRIVE_REGISTERS_SPACE 0x20 63*7d4a1addSreinoud #define DRIVE_REGISTER_BYTE_SPACING 4 64*7d4a1addSreinoud 65*7d4a1addSreinoud /* Other registers */ 66*7d4a1addSreinoud 67*7d4a1addSreinoud #define CONTROL_REGISTERS_OFFSET 0x200000 68*7d4a1addSreinoud #define CONTROL_REGISTER_SPACE 16 69*7d4a1addSreinoud 70*7d4a1addSreinoud #define IRQ_MASK_REGISTER_OFFSET 0 71*7d4a1addSreinoud #define IRQ_STATUS_REGISTER_OFFSET 0 72*7d4a1addSreinoud #define IRQ_REQUEST_REGISTER_OFFSET 1 73*7d4a1addSreinoud #define IRQ_REQUEST_REGISTER_BYTE_OFFSET (IRQ_REQUEST_REGISTER_OFFSET << 2) 74*7d4a1addSreinoud #define IRQ_CLEAR_REGISTER_OFFSET 1 75*7d4a1addSreinoud #define PRIMARY_IRQ_MASK 0x01 76*7d4a1addSreinoud #define SECONDARY_IRQ_MASK 0x02 77*7d4a1addSreinoud #define IRQ_MASK (PRIMARY_IRQ_MASK | SECONDARY_IRQ_MASK) 78*7d4a1addSreinoud 79*7d4a1addSreinoud #define VERSION_REGISTER_OFFSET 3 80*7d4a1addSreinoud #define VERSION_REGISTER_MASK 0x03 81*7d4a1addSreinoud #define VERSION_1_ID 0x00 82*7d4a1addSreinoud #define VERSION_2_ID 0x01 83*7d4a1addSreinoud 84*7d4a1addSreinoud #define PIO_MODE_CONTROL_REGISTER_OFFSET 3 85*7d4a1addSreinoud #define PIO_MODE_0 0 86*7d4a1addSreinoud #define PIO_MODE_1 1 87*7d4a1addSreinoud #define PIO_MODE_2 2 88*7d4a1addSreinoud #define PIO_MODE_3 3 89*7d4a1addSreinoud #define PIO_MODE_4 4 90