xref: /netbsd-src/lib/libpthread/arch/arm/pthread_md.h (revision 2a673dcfdbc7752f4586dab5e1ed926fd4866bbe)
1*2a673dcfSriastradh /*	$NetBSD: pthread_md.h,v 1.13 2023/05/25 14:30:02 riastradh Exp $	*/
2c62a74e6Sthorpej 
3c62a74e6Sthorpej /*
4c62a74e6Sthorpej  * Copyright (c) 2001 Wasabi Systems, Inc.
5c62a74e6Sthorpej  * All rights reserved.
6c62a74e6Sthorpej  *
7c62a74e6Sthorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8c62a74e6Sthorpej  *
9c62a74e6Sthorpej  * Redistribution and use in source and binary forms, with or without
10c62a74e6Sthorpej  * modification, are permitted provided that the following conditions
11c62a74e6Sthorpej  * are met:
12c62a74e6Sthorpej  * 1. Redistributions of source code must retain the above copyright
13c62a74e6Sthorpej  *    notice, this list of conditions and the following disclaimer.
14c62a74e6Sthorpej  * 2. Redistributions in binary form must reproduce the above copyright
15c62a74e6Sthorpej  *    notice, this list of conditions and the following disclaimer in the
16c62a74e6Sthorpej  *    documentation and/or other materials provided with the distribution.
17c62a74e6Sthorpej  * 3. All advertising materials mentioning features or use of this software
18c62a74e6Sthorpej  *    must display the following acknowledgement:
19c62a74e6Sthorpej  *	This product includes software developed for the NetBSD Project by
20c62a74e6Sthorpej  *	Wasabi Systems, Inc.
21c62a74e6Sthorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22c62a74e6Sthorpej  *    or promote products derived from this software without specific prior
23c62a74e6Sthorpej  *    written permission.
24c62a74e6Sthorpej  *
25c62a74e6Sthorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26c62a74e6Sthorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27c62a74e6Sthorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28c62a74e6Sthorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29c62a74e6Sthorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30c62a74e6Sthorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31c62a74e6Sthorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32c62a74e6Sthorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33c62a74e6Sthorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34c62a74e6Sthorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35c62a74e6Sthorpej  * POSSIBILITY OF SUCH DAMAGE.
36c62a74e6Sthorpej  */
37c62a74e6Sthorpej 
38c62a74e6Sthorpej #ifndef _LIB_PTHREAD_ARM_MD_H
39c62a74e6Sthorpej #define	_LIB_PTHREAD_ARM_MD_H
40c62a74e6Sthorpej 
41c5d359beSchristos static inline unsigned long
pthread__sp(void)42c62a74e6Sthorpej pthread__sp(void)
43c62a74e6Sthorpej {
44c5d359beSchristos 	unsigned long ret;
45c62a74e6Sthorpej 
464e11af46Sperry 	__asm volatile("mov %0, sp"
47c62a74e6Sthorpej 		: "=r" (ret));
48c62a74e6Sthorpej 
49c62a74e6Sthorpej 	return (ret);
50c62a74e6Sthorpej }
51c62a74e6Sthorpej 
5277f07e0bSmatt #if defined(__thumb__) && defined(_ARM_ARCH_6)
53*2a673dcfSriastradh #define pthread__smt_wait()	__asm __volatile(".inst.n 0xbf20") /* wfe */
5477f07e0bSmatt #define pthread__smt_wake()	__asm __volatile(".inst.n 0xbf40") /* sev */
5577f07e0bSmatt #elif !defined(__thumb__)
56*2a673dcfSriastradh #define pthread__smt_wait()	__asm __volatile(".inst 0xe320f002") /* wfe */
578837651bSmatt #define pthread__smt_wake()	__asm __volatile(".inst 0xe320f004") /* sev */
5877f07e0bSmatt #else
59*2a673dcfSriastradh #define pthread__smt_wait()	__nothing
6021ee6fc1Sriastradh #define pthread__smt_wake()	__nothing
6177f07e0bSmatt #endif
622f1e74f8Smatt 
63c62a74e6Sthorpej #define	pthread__uc_sp(ucp)	((ucp)->uc_mcontext.__gregs[_REG_SP])
64c62a74e6Sthorpej 
65c62a74e6Sthorpej /*
66c62a74e6Sthorpej  * Set initial, sane values for registers whose values aren't just
67c62a74e6Sthorpej  * "don't care".
68c62a74e6Sthorpej  */
698342d7e5Sskrll /* Set CPSR to PSR_USR32_MODE (0x10) from arm/armreg.h */
70c62a74e6Sthorpej #define _INITCONTEXT_U_MD(ucp)						\
71c62a74e6Sthorpej 	(ucp)->uc_mcontext.__gregs[_REG_CPSR] = 0x10;
72c62a74e6Sthorpej 
73c62a74e6Sthorpej #endif /* _LIB_PTHREAD_ARM_MD_H */
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