1ba340e45Schristos /* Handle cache related addresses. 2ba340e45Schristos 3*05d8e8feSchristos Copyright (C) 1996-2024 Free Software Foundation, Inc. 4ba340e45Schristos Contributed by Cygnus Solutions and Mike Frysinger. 5ba340e45Schristos 6ba340e45Schristos This file is part of the GNU simulators. 7ba340e45Schristos 8ba340e45Schristos This program is free software; you can redistribute it and/or modify 9ba340e45Schristos it under the terms of the GNU General Public License as published by 10ba340e45Schristos the Free Software Foundation; either version 3 of the License, or 11ba340e45Schristos (at your option) any later version. 12ba340e45Schristos 13ba340e45Schristos This program is distributed in the hope that it will be useful, 14ba340e45Schristos but WITHOUT ANY WARRANTY; without even the implied warranty of 15ba340e45Schristos MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ba340e45Schristos GNU General Public License for more details. 17ba340e45Schristos 18ba340e45Schristos You should have received a copy of the GNU General Public License 19ba340e45Schristos along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20ba340e45Schristos 21ba340e45Schristos #ifndef DV_M32R_CACHE_H 22ba340e45Schristos #define DV_M32R_CACHE_H 23ba340e45Schristos 24ba340e45Schristos /* Support for the MSPR register (Cache Purge Control Register) 25ba340e45Schristos and the MCCR register (Cache Control Register) are needed in order for 26ba340e45Schristos overlays to work correctly with the scache. 27ba340e45Schristos MSPR no longer exists but is supported for upward compatibility with 28ba340e45Schristos early overlay support. */ 29ba340e45Schristos 30ba340e45Schristos /* Cache Purge Control (only exists on early versions of chips) */ 31ba340e45Schristos #define MSPR_ADDR 0xfffffff7 32ba340e45Schristos #define MSPR_PURGE 1 33ba340e45Schristos 34ba340e45Schristos /* Lock Control Register (not supported) */ 35ba340e45Schristos #define MLCR_ADDR 0xfffffff7 36ba340e45Schristos #define MLCR_LM 1 37ba340e45Schristos 38ba340e45Schristos /* Power Management Control Register (not supported) */ 39ba340e45Schristos #define MPMR_ADDR 0xfffffffb 40ba340e45Schristos 41ba340e45Schristos /* Cache Control Register */ 42ba340e45Schristos #define MCCR_ADDR 0xffffffff 43ba340e45Schristos #define MCCR_CP 0x80 44ba340e45Schristos /* not supported */ 45ba340e45Schristos #define MCCR_CM0 2 46ba340e45Schristos #define MCCR_CM1 1 47ba340e45Schristos 48ba340e45Schristos #endif 49