1 /* The IGEN simulator generator for GDB, the GNU Debugger. 2 3 Copyright 2002-2024 Free Software Foundation, Inc. 4 5 Contributed by Andrew Cagney. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #ifndef IGEN_IGEN_H 23 #define IGEN_IGEN_H 24 25 /* code-generation options: */ 26 27 typedef enum 28 { 29 30 /* Transfer control to an instructions semantic code using the the 31 standard call/return mechanism */ 32 33 generate_calls, 34 35 /* Transfer control to an instructions semantic code using 36 (computed) goto's instead of the more conventional call/return 37 mechanism */ 38 39 generate_jumps, 40 41 } 42 igen_code; 43 44 typedef enum 45 { 46 nia_is_cia_plus_one, 47 nia_is_void, 48 nia_is_invalid, 49 } 50 igen_nia; 51 52 53 54 typedef struct _igen_gen_options igen_gen_options; 55 struct _igen_gen_options 56 { 57 int direct_access; 58 int semantic_icache; 59 int insn_in_icache; 60 int conditional_issue; 61 int slot_verification; 62 int delayed_branch; 63 64 /* If zeroing a register, which one? */ 65 int zero_reg; 66 int zero_reg_nr; 67 68 /* should multiple simulators be generated? */ 69 int multi_sim; 70 71 /* name of the default multi-sim model */ 72 char *default_model; 73 74 /* should the simulator support multi word instructions and if so, 75 what is the max nr of words. */ 76 int multi_word; 77 78 /* SMP? Should the generated code include SMP support (>0) and if 79 so, for how many processors? */ 80 int smp; 81 82 /* how should the next instruction address be computed? */ 83 igen_nia nia; 84 85 /* nr of instructions in the decoded instruction cache */ 86 int icache; 87 int icache_size; 88 89 /* see above */ 90 igen_code code; 91 }; 92 93 94 typedef struct _igen_trace_options igen_trace_options; 95 struct _igen_trace_options 96 { 97 int rule_selection; 98 int rule_rejection; 99 int insn_insertion; 100 int insn_expansion; 101 int entries; 102 int combine; 103 }; 104 105 typedef struct _igen_name 106 { 107 char *u; 108 char *l; 109 } 110 igen_name; 111 typedef struct _igen_module 112 { 113 igen_name prefix; 114 igen_name suffix; 115 } 116 igen_module; 117 118 typedef struct _igen_module_options 119 { 120 igen_module global; 121 igen_module engine; 122 igen_module icache; 123 igen_module idecode; 124 igen_module itable; 125 igen_module semantics; 126 igen_module support; 127 } 128 igen_module_options; 129 130 typedef struct _igen_decode_options igen_decode_options; 131 struct _igen_decode_options 132 { 133 134 /* Combine tables? Should the generator make a second pass through 135 each generated table looking for any sub-entries that contain the 136 same instructions. Those entries being merged into a single 137 table */ 138 int combine; 139 140 /* Instruction expansion? Should the semantic code for each 141 instruction, when the oportunity arrises, be expanded according 142 to the variable opcode files that the instruction decode process 143 renders constant */ 144 int duplicate; 145 146 /* Treat reserved fields as constant (zero) instead of ignoring 147 their value when determining decode tables */ 148 int zero_reserved; 149 150 /* Convert any padded switch rules into goto_switch */ 151 int switch_as_goto; 152 153 /* Force all tables to be generated with this lookup mechanism */ 154 char *overriding_gen; 155 }; 156 157 158 typedef struct _igen_warn_options igen_warn_options; 159 struct _igen_warn_options 160 { 161 162 /* Issue warning about discarded instructions */ 163 int discard; 164 165 /* Issue warning about invalid instruction widths */ 166 int width; 167 168 /* Issue warning about unimplemented instructions */ 169 int unimplemented; 170 171 }; 172 173 174 175 typedef struct _igen_options igen_options; 176 struct _igen_options 177 { 178 179 /* What does the instruction look like - bit ordering, size, widths or 180 offesets */ 181 int hi_bit_nr; 182 int insn_bit_size; 183 int insn_specifying_widths; 184 185 /* what should global names be prefixed with? */ 186 igen_module_options module; 187 188 /* See above for options and flags */ 189 igen_gen_options gen; 190 191 /* See above for trace options */ 192 igen_trace_options trace; 193 194 /* See above for include options */ 195 table_include *include; 196 197 /* See above for decode options */ 198 igen_decode_options decode; 199 200 /* Filter set to be used on the flag field of the instruction table */ 201 filter *flags_filter; 202 203 /* See above for warn options */ 204 igen_warn_options warn; 205 206 /* Be more picky about the input */ 207 error_func (*warning); 208 209 /* Model (processor) set - like flags_filter. Used to select the 210 specific ISA within a processor family. */ 211 filter *model_filter; 212 213 /* Format name set */ 214 filter *format_name_filter; 215 }; 216 217 extern igen_options options; 218 219 /* default options - hopefully backward compatible */ 220 #define INIT_OPTIONS() \ 221 do { \ 222 memset (&options, 0, sizeof options); \ 223 memset (&options.warn, -1, sizeof (options.warn)); \ 224 options.hi_bit_nr = 0; \ 225 options.insn_bit_size = default_insn_bit_size; \ 226 options.insn_specifying_widths = 0; \ 227 options.module.global.prefix.u = ""; \ 228 options.module.global.prefix.l = ""; \ 229 /* the prefixes */ \ 230 options.module.engine = options.module.global; \ 231 options.module.icache = options.module.global; \ 232 options.module.idecode = options.module.global; \ 233 options.module.itable = options.module.global; \ 234 options.module.semantics = options.module.global; \ 235 options.module.support = options.module.global; \ 236 /* the suffixes */ \ 237 options.module.engine.suffix.l = "engine"; \ 238 options.module.engine.suffix.u = "ENGINE"; \ 239 options.module.icache.suffix.l = "icache"; \ 240 options.module.icache.suffix.u = "ICACHE"; \ 241 options.module.idecode.suffix.l = "idecode"; \ 242 options.module.idecode.suffix.u = "IDECODE"; \ 243 options.module.itable.suffix.l = "itable"; \ 244 options.module.itable.suffix.u = "ITABLE"; \ 245 options.module.semantics.suffix.l = "semantics"; \ 246 options.module.semantics.suffix.u = "SEMANTICS"; \ 247 options.module.support.suffix.l = "support"; \ 248 options.module.support.suffix.u = "SUPPORT"; \ 249 /* misc stuff */ \ 250 options.gen.code = generate_calls; \ 251 options.gen.icache_size = 1024; \ 252 options.warning = warning; \ 253 } while (0) 254 255 #endif /* IGEN_IGEN_H */ 256