1*02f41505Schristos /* This file defines the interface between the RISC-V simulator and GDB. 2*02f41505Schristos 3*02f41505Schristos Copyright (C) 2005-2024 Free Software Foundation, Inc. 4*02f41505Schristos Contributed by Mike Frysinger. 5*02f41505Schristos 6*02f41505Schristos This file is part of GDB. 7*02f41505Schristos 8*02f41505Schristos This program is free software; you can redistribute it and/or modify 9*02f41505Schristos it under the terms of the GNU General Public License as published by 10*02f41505Schristos the Free Software Foundation; either version 3 of the License, or 11*02f41505Schristos (at your option) any later version. 12*02f41505Schristos 13*02f41505Schristos This program is distributed in the hope that it will be useful, 14*02f41505Schristos but WITHOUT ANY WARRANTY; without even the implied warranty of 15*02f41505Schristos MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*02f41505Schristos GNU General Public License for more details. 17*02f41505Schristos 18*02f41505Schristos You should have received a copy of the GNU General Public License 19*02f41505Schristos along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20*02f41505Schristos 21*02f41505Schristos /* Order has to match gdb riscv-tdep list. */ 22*02f41505Schristos enum sim_riscv_regnum { 23*02f41505Schristos SIM_RISCV_ZERO_REGNUM = 0, 24*02f41505Schristos SIM_RISCV_RA_REGNUM, 25*02f41505Schristos SIM_RISCV_SP_REGNUM, 26*02f41505Schristos SIM_RISCV_GP_REGNUM, 27*02f41505Schristos SIM_RISCV_TP_REGNUM, 28*02f41505Schristos SIM_RISCV_T0_REGNUM, 29*02f41505Schristos SIM_RISCV_T1_REGNUM, 30*02f41505Schristos SIM_RISCV_T2_REGNUM, 31*02f41505Schristos SIM_RISCV_S0_REGNUM, 32*02f41505Schristos #define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM 33*02f41505Schristos SIM_RISCV_S1_REGNUM, 34*02f41505Schristos SIM_RISCV_A0_REGNUM, 35*02f41505Schristos SIM_RISCV_A1_REGNUM, 36*02f41505Schristos SIM_RISCV_A2_REGNUM, 37*02f41505Schristos SIM_RISCV_A3_REGNUM, 38*02f41505Schristos SIM_RISCV_A4_REGNUM, 39*02f41505Schristos SIM_RISCV_A5_REGNUM, 40*02f41505Schristos SIM_RISCV_A6_REGNUM, 41*02f41505Schristos SIM_RISCV_A7_REGNUM, 42*02f41505Schristos SIM_RISCV_S2_REGNUM, 43*02f41505Schristos SIM_RISCV_S3_REGNUM, 44*02f41505Schristos SIM_RISCV_S4_REGNUM, 45*02f41505Schristos SIM_RISCV_S5_REGNUM, 46*02f41505Schristos SIM_RISCV_S6_REGNUM, 47*02f41505Schristos SIM_RISCV_S7_REGNUM, 48*02f41505Schristos SIM_RISCV_S8_REGNUM, 49*02f41505Schristos SIM_RISCV_S9_REGNUM, 50*02f41505Schristos SIM_RISCV_S10_REGNUM, 51*02f41505Schristos SIM_RISCV_S11_REGNUM, 52*02f41505Schristos SIM_RISCV_T3_REGNUM, 53*02f41505Schristos SIM_RISCV_T4_REGNUM, 54*02f41505Schristos SIM_RISCV_T5_REGNUM, 55*02f41505Schristos SIM_RISCV_T6_REGNUM, 56*02f41505Schristos SIM_RISCV_PC_REGNUM, 57*02f41505Schristos SIM_RISCV_FT0_REGNUM, 58*02f41505Schristos #define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM 59*02f41505Schristos SIM_RISCV_FT1_REGNUM, 60*02f41505Schristos SIM_RISCV_FT2_REGNUM, 61*02f41505Schristos SIM_RISCV_FT3_REGNUM, 62*02f41505Schristos SIM_RISCV_FT4_REGNUM, 63*02f41505Schristos SIM_RISCV_FT5_REGNUM, 64*02f41505Schristos SIM_RISCV_FT6_REGNUM, 65*02f41505Schristos SIM_RISCV_FT7_REGNUM, 66*02f41505Schristos SIM_RISCV_FS0_REGNUM, 67*02f41505Schristos SIM_RISCV_FS1_REGNUM, 68*02f41505Schristos SIM_RISCV_FA0_REGNUM, 69*02f41505Schristos SIM_RISCV_FA1_REGNUM, 70*02f41505Schristos SIM_RISCV_FA2_REGNUM, 71*02f41505Schristos SIM_RISCV_FA3_REGNUM, 72*02f41505Schristos SIM_RISCV_FA4_REGNUM, 73*02f41505Schristos SIM_RISCV_FA5_REGNUM, 74*02f41505Schristos SIM_RISCV_FA6_REGNUM, 75*02f41505Schristos SIM_RISCV_FA7_REGNUM, 76*02f41505Schristos SIM_RISCV_FS2_REGNUM, 77*02f41505Schristos SIM_RISCV_FS3_REGNUM, 78*02f41505Schristos SIM_RISCV_FS4_REGNUM, 79*02f41505Schristos SIM_RISCV_FS5_REGNUM, 80*02f41505Schristos SIM_RISCV_FS6_REGNUM, 81*02f41505Schristos SIM_RISCV_FS7_REGNUM, 82*02f41505Schristos SIM_RISCV_FS8_REGNUM, 83*02f41505Schristos SIM_RISCV_FS9_REGNUM, 84*02f41505Schristos SIM_RISCV_FS10_REGNUM, 85*02f41505Schristos SIM_RISCV_FS11_REGNUM, 86*02f41505Schristos SIM_RISCV_FT8_REGNUM, 87*02f41505Schristos SIM_RISCV_FT9_REGNUM, 88*02f41505Schristos SIM_RISCV_FT10_REGNUM, 89*02f41505Schristos SIM_RISCV_FT11_REGNUM, 90*02f41505Schristos #define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM 91*02f41505Schristos 92*02f41505Schristos #define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1 93*02f41505Schristos #define DECLARE_CSR(name, num, ...) SIM_RISCV_ ## num ## _REGNUM, 94*02f41505Schristos #include "opcode/riscv-opc.h" 95*02f41505Schristos #undef DECLARE_CSR 96*02f41505Schristos #define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1 97*02f41505Schristos 98*02f41505Schristos SIM_RISCV_LAST_REGNUM 99*02f41505Schristos }; 100