1*02f41505Schristos /* This file defines the interface between the d10v simulator and gdb. 2*02f41505Schristos 3*02f41505Schristos Copyright (C) 1999-2024 Free Software Foundation, Inc. 4*02f41505Schristos 5*02f41505Schristos This file is part of GDB. 6*02f41505Schristos 7*02f41505Schristos This program is free software; you can redistribute it and/or modify 8*02f41505Schristos it under the terms of the GNU General Public License as published by 9*02f41505Schristos the Free Software Foundation; either version 3 of the License, or 10*02f41505Schristos (at your option) any later version. 11*02f41505Schristos 12*02f41505Schristos This program is distributed in the hope that it will be useful, 13*02f41505Schristos but WITHOUT ANY WARRANTY; without even the implied warranty of 14*02f41505Schristos MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*02f41505Schristos GNU General Public License for more details. 16*02f41505Schristos 17*02f41505Schristos You should have received a copy of the GNU General Public License 18*02f41505Schristos along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19*02f41505Schristos 20*02f41505Schristos #if !defined (SIM_D10V_H) 21*02f41505Schristos #define SIM_D10V_H 22*02f41505Schristos 23*02f41505Schristos /* GDB interprets addresses as: 24*02f41505Schristos 25*02f41505Schristos 0x00xxxxxx: Physical unified memory segment (Unified memory) 26*02f41505Schristos 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) 27*02f41505Schristos 0x02xxxxxx: Physical data memory segment (On-chip data memory) 28*02f41505Schristos 0x10xxxxxx: Logical data address segment (DMAP translated memory) 29*02f41505Schristos 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) 30*02f41505Schristos 31*02f41505Schristos The remote d10v board interprets addresses as: 32*02f41505Schristos 33*02f41505Schristos 0x00xxxxxx: Physical unified memory segment (Unified memory) 34*02f41505Schristos 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) 35*02f41505Schristos 0x02xxxxxx: Physical data memory segment (On-chip data memory) 36*02f41505Schristos 37*02f41505Schristos The following translate a virtual DMAP/IMAP offset into a physical 38*02f41505Schristos memory segment assigning the translated address to PHYS. Since a 39*02f41505Schristos memory access may cross a page boundrary the number of bytes for 40*02f41505Schristos which the translation is applicable (or 0 for an invalid virtual 41*02f41505Schristos offset) is returned. */ 42*02f41505Schristos 43*02f41505Schristos enum 44*02f41505Schristos { 45*02f41505Schristos SIM_D10V_MEMORY_UNIFIED = 0x00000000, 46*02f41505Schristos SIM_D10V_MEMORY_INSN = 0x01000000, 47*02f41505Schristos SIM_D10V_MEMORY_DATA = 0x02000000, 48*02f41505Schristos SIM_D10V_MEMORY_DMAP = 0x10000000, 49*02f41505Schristos SIM_D10V_MEMORY_IMAP = 0x11000000 50*02f41505Schristos }; 51*02f41505Schristos 52*02f41505Schristos /* The simulator makes use of the following register information. */ 53*02f41505Schristos 54*02f41505Schristos enum sim_d10v_regs 55*02f41505Schristos { 56*02f41505Schristos SIM_D10V_R0_REGNUM, 57*02f41505Schristos SIM_D10V_R1_REGNUM, 58*02f41505Schristos SIM_D10V_R2_REGNUM, 59*02f41505Schristos SIM_D10V_R3_REGNUM, 60*02f41505Schristos SIM_D10V_R4_REGNUM, 61*02f41505Schristos SIM_D10V_R5_REGNUM, 62*02f41505Schristos SIM_D10V_R6_REGNUM, 63*02f41505Schristos SIM_D10V_R7_REGNUM, 64*02f41505Schristos SIM_D10V_R8_REGNUM, 65*02f41505Schristos SIM_D10V_R9_REGNUM, 66*02f41505Schristos SIM_D10V_R10_REGNUM, 67*02f41505Schristos SIM_D10V_R11_REGNUM, 68*02f41505Schristos SIM_D10V_R12_REGNUM, 69*02f41505Schristos SIM_D10V_R13_REGNUM, 70*02f41505Schristos SIM_D10V_R14_REGNUM, 71*02f41505Schristos SIM_D10V_R15_REGNUM, 72*02f41505Schristos SIM_D10V_CR0_REGNUM, 73*02f41505Schristos SIM_D10V_CR1_REGNUM, 74*02f41505Schristos SIM_D10V_CR2_REGNUM, 75*02f41505Schristos SIM_D10V_CR3_REGNUM, 76*02f41505Schristos SIM_D10V_CR4_REGNUM, 77*02f41505Schristos SIM_D10V_CR5_REGNUM, 78*02f41505Schristos SIM_D10V_CR6_REGNUM, 79*02f41505Schristos SIM_D10V_CR7_REGNUM, 80*02f41505Schristos SIM_D10V_CR8_REGNUM, 81*02f41505Schristos SIM_D10V_CR9_REGNUM, 82*02f41505Schristos SIM_D10V_CR10_REGNUM, 83*02f41505Schristos SIM_D10V_CR11_REGNUM, 84*02f41505Schristos SIM_D10V_CR12_REGNUM, 85*02f41505Schristos SIM_D10V_CR13_REGNUM, 86*02f41505Schristos SIM_D10V_CR14_REGNUM, 87*02f41505Schristos SIM_D10V_CR15_REGNUM, 88*02f41505Schristos SIM_D10V_A0_REGNUM, 89*02f41505Schristos SIM_D10V_A1_REGNUM, 90*02f41505Schristos SIM_D10V_SPI_REGNUM, 91*02f41505Schristos SIM_D10V_SPU_REGNUM, 92*02f41505Schristos SIM_D10V_IMAP0_REGNUM, 93*02f41505Schristos SIM_D10V_IMAP1_REGNUM, 94*02f41505Schristos SIM_D10V_DMAP0_REGNUM, 95*02f41505Schristos SIM_D10V_DMAP1_REGNUM, 96*02f41505Schristos SIM_D10V_DMAP2_REGNUM, 97*02f41505Schristos SIM_D10V_DMAP3_REGNUM, 98*02f41505Schristos SIM_D10V_TS2_DMAP_REGNUM 99*02f41505Schristos }; 100*02f41505Schristos 101*02f41505Schristos enum 102*02f41505Schristos { 103*02f41505Schristos SIM_D10V_NR_R_REGS = 16, 104*02f41505Schristos SIM_D10V_NR_A_REGS = 2, 105*02f41505Schristos SIM_D10V_NR_IMAP_REGS = 2, 106*02f41505Schristos SIM_D10V_NR_DMAP_REGS = 4, 107*02f41505Schristos SIM_D10V_NR_CR_REGS = 16 108*02f41505Schristos }; 109*02f41505Schristos 110*02f41505Schristos #endif 111