1 /* Target dependent code for GDB on TI C6x systems. 2 3 Copyright (C) 2010-2024 Free Software Foundation, Inc. 4 Contributed by Andrew Jenner <andrew@codesourcery.com> 5 Contributed by Yao Qi <yao@codesourcery.com> 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "linux-low.h" 23 #include "arch/tic6x.h" 24 #include "tdesc.h" 25 26 #include "nat/gdb_ptrace.h" 27 #include <endian.h> 28 29 #include "gdb_proc_service.h" 30 31 #ifndef PTRACE_GET_THREAD_AREA 32 #define PTRACE_GET_THREAD_AREA 25 33 #endif 34 35 /* There are at most 69 registers accessible in ptrace. */ 36 #define TIC6X_NUM_REGS 69 37 38 #include <asm/ptrace.h> 39 40 /* Linux target op definitions for the TI C6x architecture. */ 41 42 class tic6x_target : public linux_process_target 43 { 44 public: 45 46 const regs_info *get_regs_info () override; 47 48 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; 49 50 protected: 51 52 void low_arch_setup () override; 53 54 bool low_cannot_fetch_register (int regno) override; 55 56 bool low_cannot_store_register (int regno) override; 57 58 bool low_supports_breakpoints () override; 59 60 CORE_ADDR low_get_pc (regcache *regcache) override; 61 62 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; 63 64 bool low_breakpoint_at (CORE_ADDR pc) override; 65 }; 66 67 /* The singleton target ops object. */ 68 69 static tic6x_target the_tic6x_target; 70 71 /* Defined in auto-generated file tic6x-c64xp-linux.c. */ 72 void init_registers_tic6x_c64xp_linux (void); 73 extern const struct target_desc *tdesc_tic6x_c64xp_linux; 74 75 /* Defined in auto-generated file tic6x-c64x-linux.c. */ 76 void init_registers_tic6x_c64x_linux (void); 77 extern const struct target_desc *tdesc_tic6x_c64x_linux; 78 79 /* Defined in auto-generated file tic62x-c6xp-linux.c. */ 80 void init_registers_tic6x_c62x_linux (void); 81 extern const struct target_desc *tdesc_tic6x_c62x_linux; 82 83 union tic6x_register 84 { 85 unsigned char buf[4]; 86 87 int reg32; 88 }; 89 90 /* Return the ptrace ``address'' of register REGNO. */ 91 92 #if __BYTE_ORDER == __BIG_ENDIAN 93 static int tic6x_regmap_c64xp[] = { 94 /* A0 - A15 */ 95 53, 52, 55, 54, 57, 56, 59, 58, 96 61, 60, 63, 62, 65, 64, 67, 66, 97 /* B0 - B15 */ 98 23, 22, 25, 24, 27, 26, 29, 28, 99 31, 30, 33, 32, 35, 34, 69, 68, 100 /* CSR PC */ 101 5, 4, 102 /* A16 - A31 */ 103 37, 36, 39, 38, 41, 40, 43, 42, 104 45, 44, 47, 46, 49, 48, 51, 50, 105 /* B16 - B31 */ 106 7, 6, 9, 8, 11, 10, 13, 12, 107 15, 14, 17, 16, 19, 18, 21, 20, 108 /* TSR, ILC, RILC */ 109 1, 2, 3 110 }; 111 112 static int tic6x_regmap_c64x[] = { 113 /* A0 - A15 */ 114 51, 50, 53, 52, 55, 54, 57, 56, 115 59, 58, 61, 60, 63, 62, 65, 64, 116 /* B0 - B15 */ 117 21, 20, 23, 22, 25, 24, 27, 26, 118 29, 28, 31, 30, 33, 32, 67, 66, 119 /* CSR PC */ 120 3, 2, 121 /* A16 - A31 */ 122 35, 34, 37, 36, 39, 38, 41, 40, 123 43, 42, 45, 44, 47, 46, 49, 48, 124 /* B16 - B31 */ 125 5, 4, 7, 6, 9, 8, 11, 10, 126 13, 12, 15, 14, 17, 16, 19, 18, 127 -1, -1, -1 128 }; 129 130 static int tic6x_regmap_c62x[] = { 131 /* A0 - A15 */ 132 19, 18, 21, 20, 23, 22, 25, 24, 133 27, 26, 29, 28, 31, 30, 33, 32, 134 /* B0 - B15 */ 135 5, 4, 7, 6, 9, 8, 11, 10, 136 13, 12, 15, 14, 17, 16, 35, 34, 137 /* CSR, PC */ 138 3, 2, 139 -1, -1, -1, -1, -1, -1, -1, -1, 140 -1, -1, -1, -1, -1, -1, -1, -1, 141 -1, -1, -1, -1, -1, -1, -1, -1, 142 -1, -1, -1, -1, -1, -1, -1, -1, 143 -1, -1, -1 144 }; 145 146 #else 147 static int tic6x_regmap_c64xp[] = { 148 /* A0 - A15 */ 149 52, 53, 54, 55, 56, 57, 58, 59, 150 60, 61, 62, 63, 64, 65, 66, 67, 151 /* B0 - B15 */ 152 22, 23, 24, 25, 26, 27, 28, 29, 153 30, 31, 32, 33, 34, 35, 68, 69, 154 /* CSR PC */ 155 4, 5, 156 /* A16 - A31 */ 157 36, 37, 38, 39, 40, 41, 42, 43, 158 44, 45, 46, 47, 48, 49, 50, 51, 159 /* B16 -B31 */ 160 6, 7, 8, 9, 10, 11, 12, 13, 161 14, 15, 16, 17, 18, 19, 20, 31, 162 /* TSR, ILC, RILC */ 163 0, 3, 2 164 }; 165 166 static int tic6x_regmap_c64x[] = { 167 /* A0 - A15 */ 168 50, 51, 52, 53, 54, 55, 56, 57, 169 58, 59, 60, 61, 62, 63, 64, 65, 170 /* B0 - B15 */ 171 20, 21, 22, 23, 24, 25, 26, 27, 172 28, 29, 30, 31, 32, 33, 66, 67, 173 /* CSR PC */ 174 2, 3, 175 /* A16 - A31 */ 176 34, 35, 36, 37, 38, 39, 40, 41, 177 42, 43, 44, 45, 46, 47, 48, 49, 178 /* B16 - B31 */ 179 4, 5, 6, 7, 8, 9, 10, 11, 180 12, 13, 14, 15, 16, 17, 18, 19, 181 -1, -1, -1 182 }; 183 184 static int tic6x_regmap_c62x[] = { 185 /* A0 - A15 */ 186 18, 19, 20, 21, 22, 23, 24, 25, 187 26, 27, 28, 29, 30, 31, 32, 33, 188 /* B0 - B15 */ 189 4, 5, 6, 7, 8, 9, 10, 11, 190 12, 13, 14, 15, 16, 17, 34, 35, 191 /* CSR PC */ 192 2, 3, 193 -1, -1, -1, -1, -1, -1, -1, -1, 194 -1, -1, -1, -1, -1, -1, -1, -1, 195 -1, -1, -1, -1, -1, -1, -1, -1, 196 -1, -1, -1, -1, -1, -1, -1, -1, 197 -1, -1, -1 198 }; 199 200 #endif 201 202 static int *tic6x_regmap; 203 static unsigned int tic6x_breakpoint; 204 #define tic6x_breakpoint_len 4 205 206 /* Implementation of target ops method "sw_breakpoint_from_kind". */ 207 208 const gdb_byte * 209 tic6x_target::sw_breakpoint_from_kind (int kind, int *size) 210 { 211 *size = tic6x_breakpoint_len; 212 return (const gdb_byte *) &tic6x_breakpoint; 213 } 214 215 static struct usrregs_info tic6x_usrregs_info = 216 { 217 TIC6X_NUM_REGS, 218 NULL, /* Set in tic6x_read_description. */ 219 }; 220 221 static const struct target_desc * 222 tic6x_read_description (enum c6x_feature feature) 223 { 224 static target_desc *tdescs[C6X_LAST] = { }; 225 struct target_desc **tdesc = &tdescs[feature]; 226 227 if (*tdesc == NULL) 228 { 229 *tdesc = tic6x_create_target_description (feature); 230 static const char *expedite_regs[] = { "A15", "PC", NULL }; 231 init_target_desc (*tdesc, expedite_regs); 232 } 233 234 return *tdesc; 235 } 236 237 bool 238 tic6x_target::low_cannot_fetch_register (int regno) 239 { 240 return (tic6x_regmap[regno] == -1); 241 } 242 243 bool 244 tic6x_target::low_cannot_store_register (int regno) 245 { 246 return (tic6x_regmap[regno] == -1); 247 } 248 249 bool 250 tic6x_target::low_supports_breakpoints () 251 { 252 return true; 253 } 254 255 CORE_ADDR 256 tic6x_target::low_get_pc (regcache *regcache) 257 { 258 union tic6x_register pc; 259 260 collect_register_by_name (regcache, "PC", pc.buf); 261 return pc.reg32; 262 } 263 264 void 265 tic6x_target::low_set_pc (regcache *regcache, CORE_ADDR pc) 266 { 267 union tic6x_register newpc; 268 269 newpc.reg32 = pc; 270 supply_register_by_name (regcache, "PC", newpc.buf); 271 } 272 273 bool 274 tic6x_target::low_breakpoint_at (CORE_ADDR where) 275 { 276 unsigned int insn; 277 278 read_memory (where, (unsigned char *) &insn, 4); 279 if (insn == tic6x_breakpoint) 280 return true; 281 282 /* If necessary, recognize more trap instructions here. GDB only uses the 283 one. */ 284 return false; 285 } 286 287 /* Fetch the thread-local storage pointer for libthread_db. */ 288 289 ps_err_e 290 ps_get_thread_area (struct ps_prochandle *ph, 291 lwpid_t lwpid, int idx, void **base) 292 { 293 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) 294 return PS_ERR; 295 296 /* IDX is the bias from the thread pointer to the beginning of the 297 thread descriptor. It has to be subtracted due to implementation 298 quirks in libthread_db. */ 299 *base = (void *) ((char *) *base - idx); 300 301 return PS_OK; 302 } 303 304 static void 305 tic6x_collect_register (struct regcache *regcache, int regno, 306 union tic6x_register *reg) 307 { 308 union tic6x_register tmp_reg; 309 310 collect_register (regcache, regno, &tmp_reg.reg32); 311 reg->reg32 = tmp_reg.reg32; 312 } 313 314 static void 315 tic6x_supply_register (struct regcache *regcache, int regno, 316 const union tic6x_register *reg) 317 { 318 int offset = 0; 319 320 supply_register (regcache, regno, reg->buf + offset); 321 } 322 323 static void 324 tic6x_fill_gregset (struct regcache *regcache, void *buf) 325 { 326 auto regset = static_cast<union tic6x_register *> (buf); 327 int i; 328 329 for (i = 0; i < TIC6X_NUM_REGS; i++) 330 if (tic6x_regmap[i] != -1) 331 tic6x_collect_register (regcache, i, regset + tic6x_regmap[i]); 332 } 333 334 static void 335 tic6x_store_gregset (struct regcache *regcache, const void *buf) 336 { 337 const auto regset = static_cast<const union tic6x_register *> (buf); 338 int i; 339 340 for (i = 0; i < TIC6X_NUM_REGS; i++) 341 if (tic6x_regmap[i] != -1) 342 tic6x_supply_register (regcache, i, regset + tic6x_regmap[i]); 343 } 344 345 static struct regset_info tic6x_regsets[] = { 346 { PTRACE_GETREGS, PTRACE_SETREGS, 0, TIC6X_NUM_REGS * 4, GENERAL_REGS, 347 tic6x_fill_gregset, tic6x_store_gregset }, 348 NULL_REGSET 349 }; 350 351 void 352 tic6x_target::low_arch_setup () 353 { 354 register unsigned int csr asm ("B2"); 355 unsigned int cpuid; 356 enum c6x_feature feature = C6X_CORE; 357 358 /* Determine the CPU we're running on to find the register order. */ 359 __asm__ ("MVC .S2 CSR,%0" : "=r" (csr) :); 360 cpuid = csr >> 24; 361 switch (cpuid) 362 { 363 case 0x00: /* C62x */ 364 case 0x02: /* C67x */ 365 tic6x_regmap = tic6x_regmap_c62x; 366 tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ 367 feature = C6X_CORE; 368 break; 369 case 0x03: /* C67x+ */ 370 tic6x_regmap = tic6x_regmap_c64x; 371 tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ 372 feature = C6X_GP; 373 break; 374 case 0x0c: /* C64x */ 375 tic6x_regmap = tic6x_regmap_c64x; 376 tic6x_breakpoint = 0x0000a122; /* BNOP .S2 0,5 */ 377 feature = C6X_GP; 378 break; 379 case 0x10: /* C64x+ */ 380 case 0x14: /* C674x */ 381 case 0x15: /* C66x */ 382 tic6x_regmap = tic6x_regmap_c64xp; 383 tic6x_breakpoint = 0x56454314; /* illegal opcode */ 384 feature = C6X_C6XP; 385 break; 386 default: 387 error ("Unknown CPU ID 0x%02x", cpuid); 388 } 389 tic6x_usrregs_info.regmap = tic6x_regmap; 390 391 current_process ()->tdesc = tic6x_read_description (feature); 392 } 393 394 static struct regsets_info tic6x_regsets_info = 395 { 396 tic6x_regsets, /* regsets */ 397 0, /* num_regsets */ 398 NULL, /* disabled_regsets */ 399 }; 400 401 static struct regs_info myregs_info = 402 { 403 NULL, /* regset_bitmap */ 404 &tic6x_usrregs_info, 405 &tic6x_regsets_info 406 }; 407 408 const regs_info * 409 tic6x_target::get_regs_info () 410 { 411 return &myregs_info; 412 } 413 414 #if GDB_SELF_TEST 415 #include "gdbsupport/selftest.h" 416 417 namespace selftests { 418 namespace tdesc { 419 static void 420 tic6x_tdesc_test () 421 { 422 SELF_CHECK (*tdesc_tic6x_c62x_linux == *tic6x_read_description (C6X_CORE)); 423 SELF_CHECK (*tdesc_tic6x_c64x_linux == *tic6x_read_description (C6X_GP)); 424 SELF_CHECK (*tdesc_tic6x_c64xp_linux == *tic6x_read_description (C6X_C6XP)); 425 } 426 } 427 } 428 #endif 429 430 /* The linux target ops object. */ 431 432 linux_process_target *the_linux_target = &the_tic6x_target; 433 434 void 435 initialize_low_arch (void) 436 { 437 #if GDB_SELF_TEST 438 /* Initialize the Linux target descriptions. */ 439 init_registers_tic6x_c64xp_linux (); 440 init_registers_tic6x_c64x_linux (); 441 init_registers_tic6x_c62x_linux (); 442 443 selftests::register_test ("tic6x-tdesc", selftests::tdesc::tic6x_tdesc_test); 444 #endif 445 446 initialize_regsets_info (&tic6x_regsets_info); 447 } 448